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PDF DS28E01-100 Data sheet ( Hoja de datos )
| Número de pieza | DS28E01-100 | |
| Descripción | 1Kb Protected 1-Wire EEPROM | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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ABRIDGED DATA SHEET
DS28E01-100
1Kb Protected 1-Wire EEPROM
with SHA-1 Engine
General Description
The DS28E01-100 combines 1024 bits of EEPROM with
challenge-and-response authentication security imple-
mented with the ISO/IEC 10118-3 Secure Hash
Algorithm (SHA-1). The 1024-bit EEPROM array is con-
figured as four pages of 256 bits with a 64-bit scratch-
pad to perform write operations. All memory pages can
be write protected, and one page can be put in
EPROM-emulation mode, where bits can only be
changed from a 1 to a 0 state. Each DS28E01-100 has
its own guaranteed unique 64-bit ROM registration num-
ber that is factory lasered into the chip. The DS28E01-
100 communicates over the single-contact 1-Wire® bus.
The communication follows the standard 1-Wire protocol
with the registration number acting as the node address
in the case of a multidevice 1-Wire network.
Applications
Printer Cartridge Configuration and Monitoring
Medical Sensor Authentication and Calibration
System Intellectual Property Protection
Typical Operating Circuit
VCC
μC
RPUP
IO
DS28E01-100
GND
Pin Configurations appear at end of data sheet.
Features
♦ 1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 Bits
♦ On-Chip 512-Bit SHA-1 Engine to Compute 160-
Bit Message Authentication Codes (MACs) and to
Generate Secrets
♦ Write Access Requires Knowledge of the Secret
and the Capability of Computing and Transmitting
a 160-Bit MAC as Authorization
♦ User-Programmable Page Write Protection for
Page 0, Page 3, or All Four Pages Together
♦ User-Programmable OTP EPROM Emulation Mode
for Page 1 (“Write to 0”)
♦ Communicates to Host with a Single Digital
Signal at 15.3kbps or 90.9kbps Using 1-Wire
Protocol
♦ Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
♦ Reads and Writes Over 2.8V to 5.25V Voltage
Range from -40°C to +85°C
♦ 6-Lead TSOC and TDFN or 2-Lead TO-92 and SFN
Packages
Ordering Information
PART
DS28E01-100+
DS28E01P-100+
DS28E01P-100+T
DS28E01G-100+T&R
DS28E01Q-100+T&R
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
2 TO-92
6 TSOC
6 TSOC
2 SFN
6 TDFN-EP*
(2.5k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T and T&R = Tape and reel.
*EP = Exposed pad.
Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to
www.maximintegrated.com/DS28E01 and click on Request Full Data Sheet.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
219-0007; Rev 8; 9/12
1 page  
ABRIDGED DATA SHEET
DS28E01-100
1Kb Protected 1-Wire EEPROM
with SHA-1 Engine
TSOC
1
PIN
TDFN-EP SFN
32
221
3, 4, 5, 6 1, 4, 5, 6
—
———
TO-92
1
3
2
—
Pin Description
NAME
GND
IO
N.C.
EP
FUNCTION
Ground Reference
1-Wire Bus Interface. Open-drain signal that requires an external
pullup resistor.
Not Connected
Exposed Pad (TDFN Only). Solder evenly to the board’s ground
plane for proper operation. Refer to Application Note 3273:
Exposed Pads: A Brief Introduction for additional information.
Detailed Description
The DS28E01-100 combines 1024 bits of EEPROM
organized as four 256-bit pages, a 64-bit secret, a reg-
ister page, a 512-bit SHA-1 engine, and a 64-bit ROM
registration number in a single chip. Data is transferred
serially through the 1-Wire protocol, which requires only
a single data lead and a ground return. The DS28E01-
100 has an additional memory area called the scratch-
pad that acts as a buffer when writing to the memory,
the register page, or when installing a new secret. Data
is first written to the scratchpad from where it can be
read back. After the data has been verified, a Copy
Scratchpad command transfers the data to its final
memory location, provided that the DS28E01-100
receives a matching 160-bit MAC. The computation of
the MAC involves the secret and additional data stored
in the DS28E01-100 including the device’s registration
number. Only a new secret can be loaded without pro-
viding a MAC. The SHA-1 engine is also activated to
compute 160-bit MACs when performing an authenti-
cated read of a memory page and when computing a
new secret, instead of loading it. The DS28E01-100
understands a unique command “Refresh Scratchpad.”
Proper use of a refresh sequence after a Copy
Scratchpad operation reduces the number of weak bit
failures if the device is used in a touch environment
(see the Writing with Verification section). The refresh
sequence also provides a means to restore functionali-
ty in a device with bits in a weak state.
The device’s 64-bit ROM registration number guaran-
tees unique identification and is used to address the
device in a multidrop 1-Wire network environment,
where multiple devices reside on a common 1-Wire bus
and operate independently of each other. Applications
of the DS28E01-100 include printer cartridge configura-
tion and monitoring, medical sensor authentication and
calibration, and system intellectual property protection.
Overview
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS28E01-100. The DS28E01-100 has six main data
components: 64-bit lasered ROM, 64-bit scratchpad,
four 256-bit pages of EEPROM, register page, 64-bit
secrets memory, and a 512-bit SHA-1 engine. Figure 2
shows the hierarchic structure of the 1-Wire protocol.
The bus master must first provide one of the seven ROM
function commands: Read ROM, Match ROM, Search
ROM, Skip ROM, Resume Communication, Overdrive-
Skip ROM, or Overdrive-Match ROM. Upon completion
of an Overdrive-Skip ROM or Overdrive-Match ROM
command executed at standard speed, the device
enters overdrive mode where all subsequent communi-
cation occurs at a higher speed. The protocol required
for these ROM function commands is described in
Figure 10. After a ROM function command is success-
fully executed, the memory and SHA-1 functions
become accessible and the master can provide any
one of the 9 available function commands. The function
protocols are described in Figure 8. All data is read
and written least significant bit first.
Maxim Integrated
5
5 Page 
ABRIDGED DATA SHEET
DS28E01-100
1Kb Protected 1-Wire EEPROM
with SHA-1 Engine
SHA-1 Computation Algorithm
This description of the SHA-1 computation is adapted
from the Secure Hash Standard SHA-1 document from the
National Institute of Standards and Technology (NIST).
Refer to the full data sheet for more information. bit
Maxim Integrated
23
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