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PDF DS28E05 Data sheet ( Hoja de datos )

Número de pieza DS28E05
Descripción 1-Wire EEPROM
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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DS28E05
1-Wire EEPROM
General Description
The DS28E05 is a 112-byte user-programmable EEPROM
organized as 7 pages of 16 bytes each. Memory pages
can be individually set to write protected or EPROM
emulation mode through protection byte settings. Each
part has its own guaranteed unique 64-bit ROM identi-
fication number (ROM ID) that is factory programmed
into the chip. The DS28E05 communicates over Maxim
Integrated’s single contact 1-Wire® interface at overdrive
speed with the ROM ID acting as node address in the
case of a multiple-device 1-Wire network.
Applications
● Accessory/PCB Identification
● Medical Sensor Calibration Data Storage
● Analog Sensor Calibration
● Aftermarket Management of Consumables
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/DS28E05.related.
Features
● Single-Contact 1-Wire Interface
● 112 Bytes User EEPROM with 1K Write Cycles
● Programmable Write Protection and OTP EPROM
Emulation Modes for User Memory
● Unique Factory-Programmed 64-Bit ROM ID Number
● Communicates with Host at Up to 76.9kbps
(Overdrive Only)
● Operating Range: 2.75V to 3.63V, -40°C to +85°C
● ±8kV HBM ESD Protection (typ) on IO Pin
● 3-Pin SOT23 and 6-Pin TSOC Packages
Typical Application Circuit
VCC
µC
RPUP
IO
DS28E05
GND
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
19-6568; Rev 1; 1/14

1 page




DS28E05 pdf
DS28E05
1-Wire EEPROM
PARASITE POWER
1-Wire NET
1-Wire FUNCTION
CONTROL
64-BIT
ROM ID
Figure 1. Block Diagram
DS28E05
MEMORY
FUNCTION
CONTROL
USER EEPROM
7 PAGES OF
(128 BITS EACH)
ADMINISTRATIVE DATA
(64 BITS)
COMMAND LEVEL:
1-Wire ROM
FUNCTION COMMANDS
AVAILABLE COMMANDS:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
DS28E05
DATA FIELD AFFECTED:
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
RC-FLAG
RC-FLAG
DS28E05-SPECIFIC
MEMORY FUNCTION COMMANDS
WRITE MEMORY
READ MEMORY
USER MEMORY, ADMINISTRATIVE DATA
USER MEMORY, ADMINISTRATIVE DATA
Figure 2. Hierarchical Structure for 1-Wire Protocol
MSb
8-BIT
CRC CODE
MSb LSb MSb
Figure 3. 64-Bit ROM ID
48-BIT SERIAL NUMBER
LSb
8-BIT FAMILY CODE
(0Dh)
LSb MSb
LSb
The polynomial is X8 + X5 + X4 + 1. Additional information
about the 1-Wire Cyclic Redundancy Check is available
in Application Note  27: Understanding and Using Cyclic
Redundancy Checks with Maxim iButton® Products.
iButton is a registered trademark of Maxim Integrated
Products, Inc.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit at
a time is shifted in. After the 8th bit of the family code has
been entered, the serial number is entered. After the last
bit of the serial number has been entered, the shift reg-
ister contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
www.maximintegrated.com
Maxim Integrated 5

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DS28E05 arduino
DS28E05
1-Wire EEPROM
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E05 supports overdrive speed
of 76.9kbps (max) only and cannot be used together with
standard speed or dual-speed 1-Wire slaves on the bus.
The value of the pullup resistor primarily depends on the
1-Wire pullup voltage, network size and load conditions.
The DS28E05 requires a pullup resistor of maximum
1.5kΩ.
The idle state for the 1-Wire bus is high. If for any reason
a transaction must be suspended, the bus must be left in
the idle state if the transaction is to resume. If this does
not occur and the bus is left low for more than 16µs, one
or more devices on the bus could be reset.
Transaction Sequence
The protocol for accessing the DS28E05 through the
1-Wire port is as follows:
• Initialization
• ROM Function Command
• Memory Function Command
• Transaction Data
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS28E05 is
on the bus and is ready to operate. For more details, see
the 1-Wire Signaling section.
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the five ROM function commands that the
DS28E05 supports. All ROM function commands are 8
bits long. A list of these commands follows (see the flow-
chart in Figure 8).
Read ROM [33h]
The Read ROM command allows the bus master to read
the DS28E05’s ROM ID (8-bit family code, unique 48-bit
serial number, and 8-bit CRC). This command can only
be used if there is a single slave on the bus. If more than
one slave is present on the bus, a data collision occurs
when all slaves try to transmit at the same time (open
drain produces a wired-AND result). The family code and
48-bit serial number as read by the master are unlikely to
match the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM ID,
allows the bus master to address a specific DS28E05 on
a multidrop bus. Only the DS28E05 that exactly matches
the 64-bit ROM ID responds to the following memory
function command. All other slaves wait for a reset pulse.
This command can be used with a single or multiple
devices on the bus.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a pro-
cess of elimination to identify the ID of all slave devices.
For each bit of the ID number, starting with the least sig-
nificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choos-
ing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion, including an example.
Skip ROM [CCh]
This command can save time in a single-drop bus sys-
tem by allowing the bus master to access the memory
functions without providing the 64-bit ROM ID. If more
than one slave is present on the bus and, for example,
a read command is issued following the Skip ROM com-
mand, data collision occurs on the bus as multiple slaves
transmit simultaneously (open-drain pulldowns produce a
wired-AND result).
www.maximintegrated.com
Maxim Integrated 11

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