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PDF DS28EC20 Data sheet ( Hoja de datos )

Número de pieza DS28EC20
Descripción 20Kb 1-Wire EEPROM
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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DS28EC20
20Kb 1-Wire EEPROM
GENERAL DESCRIPTION
The DS28EC20 is a 20480-bit, 1-Wire® EEPROM
organized as 80 memory pages of 256 bits each. An
additional page is set aside for control functions.
Data is written to a 32-byte scratchpad, verified, and
then copied to the EEPROM memory. As a special
feature, blocks of eight memory pages can be write
protected or put in EPROM-Emulation mode, where
bits can only be changed from a 1 to a 0 state. The
DS28EC20 communicates over the single-conductor
1-Wire bus. The communication follows the standard
1-Wire protocol. Each device has its own unalterable
and unique 64-bit ROM registration number. The
registration number is used to address the device in
a multidrop 1-Wire net environment.
APPLICATIONS
Device Authentication
IEEE 1451.4 Sensor TEDS
Ink/Toner Cartridges
Medical Sensors
PCB Identification
Wireless Base Stations
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS28EC20+
-40°C to +85°C 3 TO-92
DS28EC20+T -40°C to +85°C 3 TO-92, T&R
DS28EC20P+ -40°C to +85°C 6 TSOC
DS28EC20P+T -40°C to +85°C 6 TSOC, T&R
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
TYPICAL OPERATING CIRCUIT
VCC
RPUP (300
to 2.2k)
PX.Y
µC
I/O
DS28EC20
GND
Commands, bytes, and modes are capitalized for clarity.
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
FEATURES
20480 Bits of Nonvolatile (NV) EEPROM
Partitioned into Eighty 256-Bit Pages
Individual 8-Page Groups of Memory Pages
(Blocks) can be Permanently Write Protected or
Put in OTP EPROM-Emulation Mode ("Write to 0")
Read and Write Access Highly Backward-
Compatible to Legacy Devices (e.g., DS2433)
256-Bit Scratchpad with Strict Read/Write
Protocols Ensures Integrity of Data Transfer
200k Write/Erase Cycle Endurance at +25°C
Unique Factory-Programmed 64-Bit Registration
Number Ensures Error-Free Device Selection
and Absolute Part Identity
Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
Communicates to Host at 15.4kbps or 90kbps
Using 1-Wire Protocol
Low-Cost TO-92 Package
Operating Range: 5V ±5%, -40°C to +85°C
Operating Range: 3.3V ±5%, 0°C to +70°C
(Standard Speed only)
IEC 1000-4-2 Level 4 ESD Protection (±8kV
Contact, ±15kV Air, Typical) for I/O Pin
PIN CONFIGURATION
28EC20
123
123
TO-92
PIN 1 ---------- GND
PIN 2 ---------- I/O
PIN 3 ---------- N.C.
FOR TAPE-AND-
REEL THE LEADS
ARE FORMED TO
100 MILS (2.54mm)
SPACING VERSUS
50 MILS (1.27mm)
FOR BULK.
BOTTOM VIEW
TSOC, Top View
1
2
6
5
PIN 1 ---------- N.C.
PIN 2 ---------- I/O
PIN 3 ---------- GND
3 4 PIN 4, 5, 6 ---- N.C.
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19-6067; Rev 5; 9/13

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DS28EC20 pdf
DS28EC20: 20Kb 1-Wire EEPROM
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System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and
current requirements during EEPROM programming. The specified value here applies to systems with only one device and with
the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00,
DS2480B, or DS2490 may be required.
Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is charged, it
does not affect normal communication.
Guaranteed by design, characterization and/or simulation only. Not production tested.
VTL, VTH, and VHY are a function of the internal supply voltage which is itself a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on I/O. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH,
and VHY.
Voltage below which, during a falling edge on I/O, a logic 0 is detected.
The voltage on I/O needs to be less or equal to VILMAX at all times the master is driving I/O to a logic 0 level.
Voltage above which, during a rising edge on I/O, a logic 1 is detected.
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic 0.
The I-V characteristic is approximately linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Interval after tRSTL during which a bus master can read a logic 0 on I/O if there is a DS28EC20 present. The power-up presence
detect pulse could be outside this interval but will be complete within 2ms after power-up.
ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold
of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming interval
should be such that the voltage at I/O is greater than or equal to 3.0V. For 3.3V±5% VPUP operation of the DS28EC20, a low-
impedance bypass of RPUP, which can be activated during programming, is required.
The tPROG interval begins tREHMAX after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from IPROG to IL.
Write-cycle endurance is degraded as TA increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as TA increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet
limit at operating temperature range is established by reliability testing.
EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated
temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
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DS28EC20 arduino
DS28EC20: 20Kb 1-Wire EEPROM
MEMORY FUNCTION COMMANDS
The Memory Function Flowchart (Figure 7) describes the protocols necessary for accessing the memory of the
DS28EC20. The target address registers TA1 and TA2 are used for both read and write. To prevent accidental
changes to the data memory or control registers the device employs a BS-flag indicating a “bad sequence”. The
communication between master and DS28EC20 takes place either at standard speed (default, OD = 0) or at
overdrive speed (OD = 1). If not explicitly set into the Overdrive mode, the DS28EC20 assumes standard speed.
For operation at overdrive speed, the DS28EC20 requires VPUP to be 5V ±5%.
WRITE SCRATCHPAD COMMAND [0Fh]
The Write Scratchpad command applies to the data memory and the writable addresses in the register page. After
issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the
data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T[4:0]. The
E/S bits E[4:0] are loaded with the starting byte offset, and increment with each subsequent byte. Effectively, E[4:0]
is the byte offset of the last full byte written to the scratchpad. Only full bytes are accepted. If the last byte is
incomplete its content is ignored and the partial byte flag PF is set. The PF flag is also set if the master ends the
command before a complete target address is transmitted. The PF and BS flags are both cleared when a complete
target address is received.
When executing the Write Scratchpad command, the CRC generator inside the DS28EC20 (Figure 13) calculates a
16-bit CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the
master. This CRC is generated using the CRC16 polynomial (X16 + X15 + X2 + 1) by first clearing the CRC
generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the target addresses
TA1 and TA2 as supplied by the master, and all the data bytes. The master can end the Write Scratchpad
command at any time. However, if the end of the scratchpad is reached (E[4:0] = 11111b), the master can send 16
read-time slots to receive the CRC generated by the DS28EC20.
If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in
memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad
is loaded with the bitwise logical AND of the transmitted data and the data already in memory.
The DS28EC20’s memory address range is 0000h to 0A3Fh. If the bus master sends a target address higher than
this, the DS28EC20’s internal circuitry sets the four most significant address bits to zero as they are shifted into the
internal address register. The Read Scratchpad command reveals the modified target address. The master
identifies such address modifications by comparing the target address read back to the target address transmitted.
If the master does not read the scratchpad, a subsequent Copy Scratchpad command does not work since the
most significant bits of the target address the master sends do not match the value the DS28EC20 expects.
READ SCRATCHPAD COMMAND [AAh]
The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After
issuing the command code, the master begins reading. The first two bytes are the target address. The next byte is
the Ending Offset/Data Status byte (E/S) followed by the scratchpad data beginning at the byte offset (T[4:0]). The
scratchpad data can be different from what the master originally sent. This is of particular importance if the target
address is within the register page or a page in either Write Protection or EPROM modes. See the Write
Scratchpad Command section for details. The master should read through the end of the scratchpad, after which it
receives an inverted CRC16, based on data as it was sent by the DS28EC20. If the master continues reading after
the CRC, all data are logic 1s.
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