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PDF 25P10A Data sheet ( Hoja de datos )
| Número de pieza | 25P10A | |
| Descripción | 1Mb 3V Serial Flash Embedded Memory | |
| Fabricantes | Micron | |
| Logotipo |  |
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M25P10A Serial Flash Embedded Memory
Features
M25P10A 1Mb 3V Serial Flash Embedded
Memory
Features
• SPI bus-compatible serial interface
• 1Mb Flash memory
• 50 MHz clock frequency (maximum)
• 2.3V to 3.6V single supply voltage
• Page program (up to 256 bytes) in 1.4ms (TYP)
• Erase capability
– Sector erase: 256Kb in 0.65s (TYP)
– Bulk erase: 1Mb in 1.7s (TYP)
• Deep power-down: 1µA (TYP)
• Electronic signature
– JEDEC-standard 2-byte signature (2011h)
– RES command, 1-byte signature (10h) for back-
ward compatibility
• More than 20 years data retention
• Automotive-certified parts available
• Packages (RoHS-compliant)
– SO8N (MN) 150 mils
– VFQFPN8 (MP) MLP8 6mm x 5mm
– UFDFN8 (MB) 2mm x 3mm
PDF: 09005aef8456656b
m25p10A.pdf - Rev. B 05/14 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
M25P10A Serial Flash Embedded Memory
Functional Description
Functional Description
The M25P10A is a 1Mb (125Kb x 8) serial Flash memory device with advanced write pro-
tection mechanisms accessed by a high-speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time using the PAGE PROGRAM
command. It is organized as 4 sectors, each containing 128 pages. Each page is 256
bytes wide. Memory can be viewed either as 512 pages or as 131,072 bytes. The entire
memory can be erased using the BULK ERASE command, or it can be erased one sector
at a time using the SECTOR ERASE command.
Figure 1: Logic Diagram
VCC
DQ0
C
S#
W#
HOLD#
DQ1
Table 1: Signal Names
Signal Name
C
DQ0
DQ1
S#
W#
HOLD#
VCC
VSS
Function
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Hold
Supply voltage
Ground
VSS
Direction
Input
Input
Output
Input
Input
Input
–
–
PDF: 09005aef8456656b
m25p10A.pdf - Rev. B 05/14 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
5 Page 
M25P10A Serial Flash Embedded Memory
Operating Features
Status Register
The status register contains a number of status and control bits that can be read or set
(as appropriate) by specific commands. For a detailed description of the status register
bits, see READ STATUS REGISTER (page 20).
Data Protection by Protocol
Non-volatile memory is used in environments that can include excessive noise. The fol-
lowing capabilities help protect data in these noisy environments.
Power on reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
PROGRAM, ERASE, and WRITE STATUS REGISTER commands are checked before they
are accepted for execution to ensure they consist of a number of clock pulses that is a
multiple of eight.
All commands that modify data must be preceded by a WRITE ENABLE command to set
the write enable latch (WEL) bit.
In addition to the low power consumption feature, the DEEP POWER-DOWN mode of-
fers extra software protection since all PROGRAM, and ERASE commands are ignored
when the device is in this mode.
Software Data Protection
Memory can be configured as read-only using the block protect bits (BP1, BP0) as
shown in the Protected Area Sizes table.
Hardware Data Protection
Hardware data protection is implemented using the write protect signal applied on the
W# pin. This freezes the status register in a read-only mode. In this mode, the block pro-
tect (BP) bits and the status register write disable bit (SRWD) are protected.
Table 3: Protected Area Sizes
Status Register Content
BP Bit 1
BP Bit 0
00
01
10
11
Protected Area
none
Upper 4th (sector 3)
Upper half (sectors 2 and 3)
All sectors (sectors 0 to 3)
Memory Content
Unprotected Area
All sectors (sectors 0 to 3)
Lower 3/4ths (sectors 0 to 2)
Lower half (sectors 0 and 1)
none
Note: 1. 0 0 = unprotected area (sectors): The device is ready to accept a BULK ERASE command
only if all block protect bits (BP1, BP0) are 0.
Hold Condition
The HOLD# signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal LOW does not terminate
any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in progress.
PDF: 09005aef8456656b
m25p10A.pdf - Rev. B 05/14 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 25P10A.PDF ] | |
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