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PDF R61523 Data sheet ( Hoja de datos )
| Número de pieza | R61523 | |
| Descripción | 360 x 640-Dot Graphics LCD Controller Driver | |
| Fabricantes | Renesas | |
| Logotipo |  |
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Specification
R61523
16,777,216–Color, 360x640-Dot Graphics LCD Controller
Driver for D-Si TFT Panel
REJxxxxxxx-xxxx
Rev.1.01
December 25, 2009
Description ......................................................................................................... 6
Features ......................................................................................................... 6
Block Diagram .................................................................................................... 9
Block Function.................................................................................................... 10
Pin Function ........................................................................................................ 13
Pad Coordinates .................................................................................................. 18
BUMP Arrangement/Alignment Mark ............................................................... 39
Recommended Resistance and Wiring Example ................................................ 40
System Interface Configuration (MIPI-DSI) ...................................................... 41
(1) Basic DSI Specification...........................................................................................................................................41
(2) DSI System Configuration.......................................................................................................................................41
(3) Lane State Definition...............................................................................................................................................42
(4) DSI-CLK Lane.........................................................................................................................................................42
1) Low Power Mode (LP-11: STOP)................................................................................ 43
2) Ultra Low Power Mode (LP-00: ULPM) ..................................................................... 43
3) High-Speed Clock Mode .............................................................................................. 44
4) High-Speed Clock Burst............................................................................................... 44
(5) DSI-D0 Data Lane ..................................................................................................................................................45
1) Power On, HWREST, soft_reset o LP-11 .................................................................. 46
2) Escape mode................................................................................................................. 46
3) Escape mode (Host>Client): Low Power Data Transmission (LPDT)......................... 46
4) Escape mode (Host>Client): Ultra Low Power State (ULPS)...................................... 46
5) Escape mode (Host>Client): Remote Application Reset (RAR) .................................. 46
6) Escape mode (Client>Host): TE-Reporting (TER) ...................................................... 47
7) Escape mode (Client>Host): Acknowledge Trigger (ACKT) ...................................... 47
8) High-Speed Data Transmission (HST)......................................................................... 47
9) Bus Turnaround (Host>Client) (BTA) ......................................................................... 47
10) Bus Turnaround (Client>Host) (BTA) ....................................................................... 47
(6) Packet Level Communication..................................................................................................................................48
1) Short Packet (SPa) Structure ........................................................................................ 48
Rev.1.01 December 25, 2009
1
Renesas SP Confidential
1 page  
R61523
Specification
NVM Control ...................................................................................................... 237
NVM Write Sequence ....................................................................................................................................................238
Absolute Maximum Rating................................................................................. 239
Electrical Characteristics .................................................................................... 240
DC characteristics ........................................................................................................................................................240
Step-up Circuit Characteristics ....................................................................................................................................243
Internal Reference Voltage ...........................................................................................................................................243
Power Supply Voltage Range .......................................................................................................................................243
Output Voltage Range...................................................................................................................................................244
Clock Characteristics....................................................................................................................................................244
Reset Timing Characteristics........................................................................................................................................245
1) Reset Timing when power is on ................................................................................... 245
2) Reset Timing during operation ..................................................................................... 245
Liquid Crystal Driver Output Characteristics..............................................................................................................246
MIPI-DBI Type B (16/8 Bits) Timing Characteristics .................................................................................................248
MIPI-DSI Interface DC Specifications .........................................................................................................................251
HS-RX Clock and Data-Clock Specifications...............................................................................................................252
LP-RX/TX Clock and Data-Clock Specifications .........................................................................................................253
Timing Diagram............................................................................................................................................................254
Revision Record.................................................................................................. 258
Rev.1.01 December 25, 2009
5
Renesas SP Confidential
5 Page 
R61523
Specification
(2) Video Image Interface (TE-signal, TE-reporting)
The R61523 supports TE as external display interface for video image.
When DBI is selected, display data is written in sync with TE signal which is generated from internal clock
to prevent flicker on the panel.
When DSI is selected, display data is written in sync with the start of the frame period by TE-reporting
function. This enables updating image data without flicker on the panel.
(3) Address Counter (AC)
The address counter (AC) gives an address to the frame memory. Address information defined by CDR and
PR is transferred to the AC. The AC is automatically updated plus or minus 1 as the R61523 writes/reads
data to/from the frame memory. Display data can be written only to the rectangular area defined in the
frame memory.
(4) Frame Memory
The R61523 incorporates the frame memory that has a capacity of 691,200 bytes, which can store bit-
pattern data of 360RGB x 640 graphics display at maximum using 24 bits to represent one pixel.
(5) Grayscale Voltage Generating Circuit
The grayscale voltage generating circuit generates liquid crystal drive voltage according to the grayscale
setting value in the J correction register. RGB-separate J correction setting enables the maximum of
16,777,216-color display.
(6) LCD Drive Power Supply Circuit
The LCD drive power supply circuit generates VREG1, VGH, VGL, VCL, and VCOM levels to drive the
liquid crystal panel.
(7) Timing Generator
The timing generator is used to generate timing signals for the operation of internal circuits such as frame
memory. The timing signals for display operation such as frame memory read and frame memory access
by host processor are generated separately so that the two do not interfere with each other.
(8) Oscillator (OSC)
The R61523 incorporates an oscillator. The frame frequency can be adjusted by commands.
(9) LCD Driver Circuit
The LCD driver circuit consists of a 1080-channel source driver (S[1:1080]). The display pattern data is
latched when 360RGB pixels of data are input. The voltage is output from the source driver according to
the latched data. The shift direction of source output can be changed by setting SS bit (C0h). The gate
driver circuit consists of a 640-channel gate driver (G[1:640]). The voltage at VGH level or VGL level is
output from the gate driver. The shift direction of gate output can be changed by GS bit (C0h). The scan
mode of the gate driver can be changed by SM bit (C0h) according to the mounting condition.
Rev.1.01 December 25, 2009
11
Renesas SP Confidential
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet R61523.PDF ] | |
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