PDF SAM9260 Data sheet ( Hoja de datos )

Número de pieza	SAM9260
Descripción	AT91SAM ARM-based Embedded MPU
Fabricantes	ATMEL Corporation
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AT91SAM ARM-based Embedded MPU SAM9260 Features • 180 MHz ARM926EJ-S™ ARM® Thumb® Processor – 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU • Memories – 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC – Two 4-kbyte internal SRAM, single-cycle access at system speed – One 32-kbyte internal ROM, embedding bootstrap routine • Peripherals – ITU-R BT. 601/656 Image Sensor Interface – USB Device and USB Host with dedicated On-Chip Transceiver – 10/100 Mbps Ethernet MAC Controller – One High Speed Memory Card Host – Two Master/Slave Serial Peripheral Interfaces – Two Three-channel 32-bit Timer/Counters – One Synchronous Serial Controller – One Two-wire Interface – Four USARTs – Two UARTs – 4-channel 10-bit ADC • System – 90 MHz six 32-bit layer AHB Bus Matrix – 22 Peripheral DMA Channels – Boot from NAND Flash, DataFlash® or serial DataFlash – Reset Controller with On-Chip Power-on Reset – Selectable 32,768 Hz Low-Power and 3-20 MHz Main Oscillator – Internal Low-Power 32 kHz RC Oscillator – One PLL for the system and one PLL optimized for USB – Two Programmable External Clock Signals – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real Time Timer • I/O – Three 32-bit Parallel Input/Output Controllers – 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os • Package – 217-ball BGA, 0.8 mm pitch – 208-pin QFP, 0.5 mm pitch This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6221LS–ATARM–15-Oct-12 1 page Table 3-1. Signal Description List (Continued) Signal Name Function NRST TST Microcontroller Reset Test Mode Select Reset/Test Type I/O Input Active Level Low BMS DRXD DTXD IRQ0 - IRQ2 FIQ PA0 - PA31 PB0 - PB31 PC0 - PC31 D0 - D31 A0 - A25 NWAIT NCS0 - NCS7 NWR0 - NWR3 NRD NWE NBS0 - NBS3 CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1 Boot Mode Select Input Debug Unit - DBGU Debug Receive Data Input Debug Transmit Data Output Advanced Interrupt Controller - AIC External Interrupt Inputs Input Fast Interrupt Input Input PIO Controller - PIOA - PIOB - PIOC Parallel IO Controller A I/O Parallel IO Controller B I/O Parallel IO Controller C I/O External Bus Interface - EBI Data Bus I/O Address Bus Output External Wait Signal Input Static Memory Controller - SMC Chip Select Lines Output Write Signal Output Read Signal Output Write Enable Output Byte Mask Signal Output CompactFlash Support CompactFlash Chip Enable Output CompactFlash Output Enable Output CompactFlash Write Enable Output CompactFlash IO Read Output CompactFlash IO Write Output CompactFlash Read Not Write Output CompactFlash Chip Select Lines Output Low Low Low Low Low Low Low Low Low Low Low Low Comments Pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. No pull-up resistor BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP0. Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset 0 at reset SAM9260 [SUMMARY] 6221LS–ATARM–15-Oct-12 5 5 Page 4.3 217-ball LFBGA Package Figure 11-1 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in the section “SAM9260 Mechanical Characteristics” of the datasheet. 4.4 217-ball LFBGA Pinout Table 4-2. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 Pinout for 217-ball LFBGA Package Signal Name Pin Signal Name CFIOW/NBS3/NWR3 D5 A5 NBS0/A0 D6 GND NWR2/NBS2/A1 D7 A10 A6 D8 GND A8 D9 VDDCORE A11 D10 GND A13 D11 VDDIOM BA0/A16 D12 GND A18 D13 DDM A21 D14 HDPB A22 D15 NC CFWE/NWE/NWR0 D16 VDDBU CFOE/NRD D17 XIN32 NCS0 E1 D10 PC5 E2 D5 PC6 E3 D3 PC4 E4 D4 SDCK E14 HDPA CFIOR/NBS1/NWR1 E15 HDMA SDCS/NCS1 E16 GNDBU SDA10 E17 XOUT32 A3 F1 D13 A7 F2 SDWE A12 F3 D6 A15 F4 GND A20 F14 OSCSEL NANDWE F15 BMS PC7 F16 JTAGSEL PC10 F17 TST PC13 G1 PC15 PC11 G2 D7 PC14 G3 SDCKE PC8 G4 VDDIOM WKUP G14 GND D8 G15 NRST D1 G16 RTCK CAS G17 TMS A2 H1 PC18 A4 H2 D14 A9 H3 D12 A14 H4 D11 BA1/A17 H8 GND A19 H9 GND NANDOE H10 GND PC9 H14 VDDCORE PC12 H15 TCK DDP H16 NTRST HDMB H17 PB18 NC J1 PC19 VDDIOP0 J2 PC17 SHDN J3 VDDIOM D9 J4 PC16 D2 J8 GND RAS J9 GND D0 J10 GND Pin Signal Name J14 TDO J15 PB19 J16 TDI J17 PB16 K1 PC24 K2 PC20 K3 D15 K4 PC21 K8 GND K9 GND K10 GND K14 PB4 K15 PB17 K16 GND K17 PB15 L1 GND L2 PC26 L3 PC25 L4 VDDIOP0 L14 PA28 L15 PB9 L16 PB8 L17 PB14 M1 VDDCORE M2 PC31 M3 GND M4 PC22 M14 PB1 M15 PB2 M16 PB3 M17 PB7 N1 XIN N2 VDDPLL N3 PC23 N4 PC27 N14 PA31 N15 PA30 N16 PB0 N17 PB6 P1 XOUT P2 VDDPLL P3 PC30 P4 PC28 P5 PB11 P6 PB13 P7 PB24 P8 VDDIOP1 P9 PB30 P10 PB31 P11 PA1 P12 PA3 P13 PA7 P14 PA9 P15 PA26 P16 PA25 Pin Signal Name P17 PB5 R1 NC R2 GNDANA R3 PC29 R4 VDDANA R5 PB12 R6 PB23 R7 GND R8 PB26 R9 PB28 R10 PA0 R11 PA4 R12 PA5 R13 PA10 R14 PA21 R15 PA23 R16 PA24 R17 PA29 T1 PLLRCA T2 GNDPLL T3 PC0 T4 PC1 T5 PB10 T6 PB22 T7 GND T8 PB29 T9 PA2 T10 PA6 T11 PA8 T12 PA11 T13 VDDCORE T14 PA20 T15 GND T16 PA22 T17 PA27 U1 GNDPLL U2 ADVREF U3 PC2 U4 PC3 U5 PB20 U6 PB21 U7 PB25 U8 PB27 U9 PA12 U10 PA13 U11 PA14 U12 PA15 U13 PA19 U14 PA17 U15 PA16 U16 PA18 U17 VDDIOP0 SAM9260 [SUMMARY] 6221LS–ATARM–15-Oct-12 11 11 Page

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