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PDF XC3S200A Data sheet ( Hoja de datos )

Número de pieza XC3S200A
Descripción Spartan-3A FPGA Family
Fabricantes Xilinx 
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0
Spartan-3A FPGA Family:
Data Sheet
DS529 August 19, 2010
0 0 Product Specification
Module 1:
Introduction and Ordering Information
DS529-1 (v2.0) August 19, 2010
• Introduction
• Features
• Architectural and Configuration Overview
• General I/O Capabilities
• Production Status
• Supported Packages and Package Marking
• Ordering Information
Module 2:
Spartan-3A FPGA Family: Functional
Description
DS529-2 (v2.0) August 19, 2010
The functionality of the Spartan®-3A FPGA family is
described in the following documents.
UG331: Spartan-3 Generation FPGA User Guide
• Clocking Resources
• Digital Clock Managers (DCMs)
• Block RAM
• Configurable Logic Blocks (CLBs)
- Distributed RAM
- SRL16 Shift Registers
- Carry and Arithmetic Logic
• I/O Resources
• Embedded Multiplier Blocks
• Programmable Interconnect
• ISE® Design Tools and IP Cores
• Embedded Processing and Control Solutions
• Pin Types and Package Overview
• Package Drawings
• Powering FPGAs
• Power Management
UG332: Spartan-3 Generation Configuration User Guide
• Configuration Overview
• Configuration Pins and Behavior
• Bitstream Sizes
• Detailed Descriptions by Mode
- Master Serial Mode using Platform Flash PROM
- Master SPI Mode using Commodity Serial Flash
- Master BPI Mode using Commodity Parallel Flash
- Slave Parallel (SelectMAP) using a Processor
- Slave Serial using a Processor
- JTAG Mode
• ISE iMPACT Programming Examples
• MultiBoot Reconfiguration
• Design Authentication using Device DNA
UG334: Spartan-3A/3AN FPGA Starter Kit User Guide
Module 3:
DC and Switching Characteristics
DS529-3 (v2.0) August 19, 2010
• DC Electrical Characteristics
• Absolute Maximum Ratings
• Supply Voltage Specifications
• Recommended Operating Conditions
• Switching Characteristics
• I/O Timing
• Configurable Logic Block (CLB) Timing
• Multiplier Timing
• Block RAM Timing
• Digital Clock Manager (DCM) Timing
• Suspend Mode Timing
• Device DNA Timing
• Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS529-4 (v2.0) August 19, 2010
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
For more information on the Spartan-3A FPGA family, go to
www.xilinx.com/spartan3a
Spartan-3A FPGA
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Status
Production
Production
Production
Production
Production
© Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529 August 19, 2010
Product Specification
www.xilinx.com
1

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XC3S200A pdf
Introduction and Ordering Information
Configuration
I/O Capabilities
Spartan-3A FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
• Master Serial from a Xilinx Platform Flash PROM
• Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
• Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
• Slave Serial, typically downloaded from a processor
• Slave Parallel, typically downloaded from a processor
• Boundary Scan (JTAG), typically downloaded from a
processor or system tester
Furthermore, Spartan-3A FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
Additionally, each Spartan-3A FPGA contains a unique,
factory-programmed Device DNA identifier useful for
tracking purposes, anti-cloning designs, or IP protection.
The Spartan-3A FPGA SelectIO interface supports many
popular single-ended and differential standards. Table 2
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional
input-only pins as indicated in Table 2.
Spartan-3A FPGAs support the following single-ended
standards:
• 3.3V low-voltage TTL (LVTTL)
• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
• 3.3V PCI at 33 MHz or 66 MHz
• HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
• SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
Spartan-3A FPGAs support the following differential
standards:
• LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
• Bus LVDS I/O at 2.5V
• TMDS I/O at 3.3V
• Differential HSTL and SSTL I/O
• LVPECL inputs at 2.5V or 3.3V
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Package
Body Size
(mm)
Device
XC3S50A
XC3S200A
VQ100
VQG100
14 x 14(2)
User
68
(13)
68
(13)
Diff
60
(24)
60
(24)
XC3S400A
-
-
XC3S700A
-
-
XC3S1400A -
-
TQ144
TQG144
20 x 20(2)
User
108
(7)
Diff
50
(24)
--
--
--
--
FT256
FTG256
17 x 17
User
144
(32)
195
(35)
195
(35)
161
(13)
161
(13)
Diff
64
(32)
90
(50)
90
(50)
74
(36)
74
(36)
FG320
FGG320
19 x 19
User Diff
--
248 112
(56) (64)
251 112
(59) (64)
--
--
FG400
FGG400
21 x 21
User Diff
--
--
311 142
(63) (78)
311 142
(63) (78)
--
FG484
FGG484
23 x 23
User Diff
--
--
--
372 165
(84) (93)
375 165
(87) (93)
FG676
FGG676
27 x 27
User Diff
--
--
--
--
502 227
(94) (131)
Notes:
1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
2. The footprints for the VQ/TQ packages are larger than the package body. See the Package Drawings for details.
DS529-1 (v2.0) August 19, 2010
www.xilinx.com
5

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XC3S200A arduino
DS529-3 (v2.0) August 19, 2010
64
Spartan-3A FPGA Family:
DC and Switching Characteristics
0 Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance: Initial estimates are based on simulation, early
characterization, and/or extrapolation from the
characteristics of other families. Values are subject to
change. Use as estimates, not for production.
Preliminary: Based on characterization. Further changes
are not expected.
Production: These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all Spartan®-3A devices. AC and DC characteristics
are specified using the same numbers for both
commercial and industrial grades.
Absolute Maximum Ratings
Stresses beyond those listed under Table 4: Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
Table 4: Absolute Maximum Ratings
Symbol
Description
Conditions
Min Max Units
VCCINT
VCCAUX
VCCO
VREF
VIN
IIK
Internal supply voltage
Auxiliary supply voltage
Output driver supply voltage
Input reference voltage
Voltage applied to all User I/O pins and
dual-purpose pins
Voltage applied to all Dedicated pins
Input clamp current per I/O pin
Driver in a high-impedance state
–0.5V < VIN < (VCCO + 0.5V)(1)
Human body model
–0.5
–0.5
–0.5
–0.5
–0.95
–0.5
1.32
3.75
3.75
VCCO + 0.5
4.6
4.6
±100
±2000
V
V
V
V
V
V
mA
V
VESD Electrostatic Discharge Voltage
Charged device model
Machine model
±500
V
±200
V
TJ
TSTG
Junction temperature
Storage temperature
– 125 °C
–65 150 °C
Notes:
1. Upper clamp applies only when using PCI IOSTANDARDs.
2. For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
© Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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