DataSheet.es    


PDF SE4110L Data sheet ( Hoja de datos )

Número de pieza SE4110L
Descripción GPS Receiver IC
Fabricantes SiGe Semiconductor 
Logotipo SiGe Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de SE4110L (archivo pdf) en la parte inferior de esta página.


Total 22 Páginas

No Preview Available ! SE4110L Hoja de datos, Descripción, Manual

SE4110L
GPS Receiver IC
Applications
ƒ High sensitivity / low power GPS and A-GPS
applications
ƒ Portable navigation devices, mobile phones and
GPS peripheral devices
ƒ Telematics equipment
Features
ƒ Single-conversion L1-band GPS radio with
integrated IF filter
ƒ Integrated LNA; 1.6 dB typ. noise figure
ƒ Low RF system noise figure; 2.3 dB typ.
ƒ Low 10 mA operating current with 2.7-3.3 V supply;
8 mA with internal LNA disabled
ƒ Standby current <10 µA
ƒ Fully Integrated PLL, compatible with 13, 16.368,
19.5 and 26 MHz reference frequencies
ƒ 2-bit SIGN & MAG Digital IF output
ƒ Integrated VCO and resonator
ƒ I/O supply range extends down to 1.7 V
ƒ 4 x 4 mm 24 pin QFN
ƒ Pb-free, RoHS compliant and Halogen-free
Ordering Information
Part No.
Package
Remark
SE4110L-R 24 Pin QFN Shipped in Tape & Reel
Product Description
The SE4110L is a highly integrated GPS receiver
offering high performance and low-power operation in a
wide range of low-cost applications. It is particularly
well-suited to mobile phone and high sensitivity L1-band
GPS and A-GPS systems.
The SE4110L includes an on-chip LNA and a low IF
receiver with a linear AGC and 2-bit analogue-to-digital
converter (ADC). The receiver incorporates a fully
integrated image reject mixer so no SAW filter is
required in many applications. There is also an on-chip
IF filter.
The SE4110L supports a wide range of reference
frequencies, addressing both traditional GPS systems
and emerging mobile phone applications. The
synthesizer is highly integrated requiring only two
passive components to implement an off-chip loop filter.
The SE4110L is optimized for the lowest possible
power consumption consistent with the very low
external component count.
The SE4110L incorporates current-controlled low-
spurious output buffers which may optionally be run
from a separate external supply to interface to low
voltage systems. The buffers supply sufficient current to
drive most baseband devices directly.
Functional Block Diagram
Optional
filter
LNA_OUT
MIX_IN
VAGC
LNA_IN
Buffer
LNA
IF Filter
~~~
-45°
+45°
AGC
Controller
ADC
IQ
SE4110
Quadrature
y2
VCO
~
Feedback
Divider
Phase/Frequency
Detector
Clock
select
Reference
Divider
Chip
control
VTUNE
~ Reference
Oscillator
/ Buffer
PLL Loop
Filter
XTAL1
XTAL2
AGC_DIS
MAG
SIGN
CLK_OUT
FREF2
FREF1
FREF0
RX_EN
OSC_EN
RVI
DST-00002 ƒ Rev 6.4 ƒ May-26-2009
1 of 22

1 page




SE4110L pdf
SE4110L
GPS Receiver IC
Functional Description
LNA
The internal LNA allows a high-performance, low-
power GPS receiver to be completed without using
any additional active components.
The GPS L1 input signal which is applied to LNA_IN
(pin 3), is a spread-spectrum signal centered on
1575.42 MHz with a 1.023 Mbps BPSK modulation.
The signal level at the antenna is typically -130 dBm
in open-sky conditions, dropping to below -150 dBm
in masked signal areas (e.g. indoors). The LNA noise
figure is the largest contributor to the sensitivity so it is
an important parameter; the lower, the better.
The LNA input requires a minimum of external
matching components to achieve good RF gain with
minimal noise figure: only a single series inductor and
single shunt capacitor are required. The input requires
a DC blocking capacitor if circuitry prior to the LNA
has a DC bias. Although attention should be paid to
track lengths and interference throughout the design,
the LNA input matching circuit is the only RF circuit
critically sensitive to layout.
The LNA output includes internal 50 : matching for
connection to the mixer input, either directly or via an
optional external filter.
In applications where the internal LNA is not required,
the LNA can be disabled by connecting VCC_LNA
(pin 1) to GND. This will save approximately 1.9 mA
of active current.
Mixer RF Input
The mixer RF input, MIX_IN (pin 21), is a single-
ended 50 ȍ input designed to interface either to
LNA_OUT (pin 24) or to the output of an external
filter. An external active antenna can also be
connected to the mixer input.
The image reject mixer ensures that the receiver’s full
sensitivity is achieved without an external filter. For
applications where additional selectivity is required,
an external filter can be added between the
LNA_OUT and MIX_IN pins.
IF Filter
The SE4110L includes a fully integrated Intermediate
Frequency (IF) filter which provides excellent
interference rejection with no additional external
components. The filter has a 3rd order Butterworth
bandpass response.
The bandpass response has a nominal bandwidth of
2.2 MHz; the nominal center frequency is preset to
4.092 MHz. These parameters ensure very low
implementation loss in all frequency plan
configurations.
AGC and ADC
The SE4110L features a linear IF chain with 2-bit
SIGN / MAG ADC. SIGN is on pin 10, and MAG on
pin 11.
An Automatic Gain Control (AGC) system is included.
This provides over 40 dB of gain control range so that
the output signal level is held at an optimum level at
the input of the ADC.
The MAG data controls the AGC loop, such that the
MAG bit is active (HIGH) for approximately 33 % of
the time.
The SIGN and MAG signals are latched by the rising
edge of the sample clock, CLK_OUT (pin 9). The
SIGN and MAG signals are best sampled by the GPS
baseband IC on the rising edge of CLK_OUT, for
optimum sample and hold in the ADC.
The AGC time constant is determined by a single
external capacitor, connected between VAGC (pin 5),
and VSSN / GND. The settling-time of the AGC is
within 10ms with a 10nF capacitor.
The AGC system also features a control-inhibit
facility, via AGC_DIS (pin 6). By connecting AGC_DIS
to VDDN, the internal AGC controller is inhibited, and
the gain held at the level set prior to the inhibition.
While the AGC controller is inhibited, it is possible to
control the AGC gain from an external source by
applying a low-impedance voltage to VAGC (pin 5).
PLL and Loop Filter
The entire phase-locked loop (PLL) generating the
local oscillator for the mixer is contained on-chip, with
the exception of the PLL loop filter.
A PLL loop filter can be implemented by attaching a
series capacitor (220 pF) and a resistor (33 kȍ)
between VTUNE (pin 18) and GND / VSSN. The PLL
follows a classic 3rd-order response; this is achieved
in conjunction with an on-chip 10 pF capacitor
connected between VTUNE and GND / VSSN.
Typical PLL Loop Bandwidth is set to be 200 kHz.
The reference frequency for the PLL may be supplied
either externally or using the on-chip crystal oscillator.
DST-00002 ƒ Rev 6.4 ƒ May-26-2009
5 of 22

5 Page





SE4110L arduino
SE4110L
GPS Receiver IC
AC Electrical Characteristics, VCO and Local Oscillator
Conditions: VCC = VDD = 3.3 V, TA = 25 qC
Symbol
Parameter
Note Min.
LO Centre Frequency
(16.368 MHz reference)
fLO
LO Centre Frequency
(13, 19.5 & 26 MHz reference)
1-
1-
L1k LO SSB Phase Noise At 1 kHz Offset
2-
L10k LO SSB Phase Noise At 10 kHz Offset
2-
L100k LO SSB Phase Noise At 100 kHz Offset 2 -
Sample clock output frequency
(16.368 MHz reference)
fCLK
Sample clock output frequency
(13, 19.5 & 26 MHz reference)
--
--
Note: (1) VCO frequency operates at 2x LO frequency.
(2) Typical PLL Loop Bandwidth = 200 kHz
Typ.
1571.328
1579.5
-86
-88
-83
16.368
19.5
Max.
-
Unit
MHz
- MHz
- dBc/Hz
- dBc/Hz
- dBc/Hz
- MHz
- MHz
AC Electrical Characteristics, Crystal Oscillator
Conditions: VCC = VDD = 3.3 V, TA = 25 qC
Symbol
Parameter
Note Min.
Typ.
Max.
fXTAL
Oscillator Frequency
- 13
-
26
RX
CLOAD
PX
tSTART
Recommended crystal parameters
ESR
Load capacitance
Drive power specification
Oscillator Startup Time To 95 % Of Final
Amplitude And Within 10 ppm Of Final
Frequency
1, 2
50
--
10
2
80
-
VIN External oscillator drive level
- 0.2
1
-
CIN External oscillator Input Load Capacitance 3 -
0.5
-
Note: (1) Recommended crystal parameters assume a parallel, fundamental mode crystal is used.
(2) Valid for a 13 MHz crystal.
(3) Connected TCXO to XTAL1 (pin 15) input
Unit
MHz
:
pF
µW
ms
V p-p
pF
DST-00002 ƒ Rev 6.4 ƒ May-26-2009
11 of 22

11 Page







PáginasTotal 22 Páginas
PDF Descargar[ Datasheet SE4110L.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
SE4110LGPS Receiver ICSiGe Semiconductor
SiGe Semiconductor
SE4110L-RGPS Receiver ICSiGe Semiconductor
SiGe Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar