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PDF CH7516 Data sheet ( Hoja de datos )

Número de pieza CH7516
Descripción 4 Lane DP to 4 Channel LVDS Monitor Controller
Fabricantes Chrontel 
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Chrontel
CH7516
Brief Datasheet
CH7516 4 Lane DP to 4 Channel LVDS Monitor Controller
FEATURES
GENERAL DESCRIPTION
Supports DisplayPort specification version 1.1a.
Support 4 Main Link Lanes at either 1.62Gb/s or
2.7Gb/s link rate
Supports input color depth 6/8/10-bit per pixel in RGB
format
Support VESA and CEA timing standards up to
QSXGA 2560x2048 @ 60Hz or 4Kx2K@24/30Hz for
2D, and Full HD 1920x1080 @120Hz for 3D(L/R eye
frame at 60Hz each), with 10 bit graphic color depth
Support HDCP Amendment for DisplayPort Rev. 1.1a
with external key storage
Support Single Port, Dual Port and Quad port LVDS
Chrontel’s CH7516 is a low-cost, low-power
semiconductor device that translates the DisplayPort
signal to the LVDS in form of RGB/YCbCr 4:4:4/YCbCr
4:2:2. This innovative DisplayPort receiver with
integrated 4 channel LVDS transmitters is specially
designed to target the All-In-One PC and the notebook
market segments. Leveraging the DisplayPort’s unique
source/sink “Link Training” routine, the CH7516 is
capable of instantly bring up the video display to the LCD
when the initialization process is completed between
CH7516 and the graphic chip.
output interface with 6/8/10-bit color depth up to
400MHz pixel rate
Support both OpenLDI (or JEIDA), SPWG (or VESA)
and non-JEITA (10-bit only) bit mapping for LVDS
application
Flexible LVDS output pins swapping
2 channel IIS/ S/PDIF audio output
Support Dynamic Backlight luminance Control by the
command through AUX channel, or through the
interface of PWM in/out and Backlight Brightness
Control (OSD display)
The CH7516 is designed to meet the DisplayPort
Specification version 1.1a. The 4 DisplayPort Main Link
Lanes receiver supports input with data rate running at
either 1.62Gb/s or 2.7Gb/s, and can accept digital RGB
signal for LVDS output up to QSXGA 2560x2048@60Hz
or 4Kx2K@24/30Hz. With advanced 3D processing
module integrated, The CH7516 can support up to
1920x1080@120Hz 3D display mode, with
programmable emitter control signal and 3D LCD panel’s
backlight control signal output.
Support PWM bypass through and on-chip PWM
generation (range 30~100%)
Support Panel selection function with external hardware
configuration
Initiated and controlled by firmware which is loaded
from External BOOT ROM automatically upon power
up.
BOOT ROM data updated through I2C bus or AUX
Channel
Support dynamic refresh rate (DDR) switching
Supports Enhanced Framing Mode
3 work modes: connect 27MHz crystal, inject 27MHz
or 14.318MHz clock
Programmable LCD panel power sequence
The Backlight Enable control and the PWM are the two
kinds of backlight control functions designed in the
CH7516 Panel power control module. The brightness
control commands sent through AUX Channel can be
dynamically translated by CH7516 and converted into
LCD backlight control signal. Alternatively, the
brightness control commands can be input from the PWM
in and GOIO pin of Backlight Brightness Control. The
CH7516 will save the last setting of brightness level into
the external BOOT ROM and restore it upon power up.
The CH7516 can dynamically adjust backlight brightness
according to video stream to save power consumption and
it supports OSD display in this way.
Hot Plug Detection
Support chip power down by GPIO pin
Support power management mechanism through AUX
Channel
EMI reduction capability for DP input and LVDS
output. Spread spectrum control is available for
transmitting LVDS signal
Achieve bit error rate <10-9 for raw transport data per
lane and symbol error rate <10-12 for control data
Low power consumption
Offered in a 128-pin TQFP package (14 x 14mm)
The CH7516 will immediately convert the DisplayPort
signal to LVDS output after DisplayPort Link Training is
completed. This feature can be achieved by loading the
panel’s EDID and the CH7516’s configuration settings in
the serial external BOOT ROM connected to the CH7516.
During system power-up and upon completion of the
DisplayPort Link Training through AUX Channel,
CH7516 will generate LVDS signal according to the
panel power-up timing sequencing stored in the external
BOOT ROM.
APPLICATION
An advanced Power Management Unit (PMU) is
incorporated in CH7516, which is specially designed to
reduce power consumption in normal operation.
209-1000-063 Rev 0.3
2013-1-25
1

1 page




CH7516 pdf
CHRONTEL
CH7516
1.2 Pin Description
Table 1: CH7516 Pin Description
Pin #
Type
Symbol
1 In RB
2 RESERVED
Description
Reset* Input (Internal pull-up)
When this pin is pull low, the device is held in the power-on reset condition.
When this pin is pull high, reset is controlled through the serial port register.
Reserved Pin
6,7 In XO, XI
27MHz Crystal Input
10 In REFCK
11,12,83,84 In/Out GPIO[3:0]
Clock Input
This pin is used as clock input pin when injecting 27MHz/14.318MHz clock
to CH7516
General Purpose Input/Output
13~20,75~82
NC
Not Connected
23~34
35~46
49~60
61~72
87
Out LC3P/N,
The Fourth Channel LVDS Output
LD19P/N~LD15P/
N
Out LC2P/N,
The Third Channel LVDS Output
LD14P/N~LD10P/
N
Out LC1P/N,
The Second Channel LVDS Output
LD9P/N~LD5P/N
Out LC0P/N,
The First Channel LVDS Output
LD4P/N~LD0P/N
Out MCLK
I2S Master Clock Output
88 Out SDATA I2S Data Output
Out SPDIF
S/PDIF Output
89 Out WS
I2S Word Select
90 Out SCLK
I2S Clock Output
91
92~94
95~96
98
In PWRDN
In PSEL[2:0]
In/Out AUXN/P
Out VDDEN
Power Down Control
CH7516 enters/exit power down state when receiving active low pulse from
this pin
LVDS Panel Selection
These pins should be pull-up or pull-down in the application, instead of
floating.
Aux channel differential input/output
These two pins are DisplayPort AUX Channel control, which supports a half-
duplex, bi-directional AC-coupled differential signal.
LCD Panel VCC Enable
99
Out BKLR_EN
LCD Panel Right Eye Backlight Enable in 3D Mode
LCD Panel Backlight Enable in 2D Mode
100
Out BKLL_EN
LCD Panel Left Eye Backlight Enable
102 Out PWM_OUT PWM output for backlight brightness dimming
103
In PWM_IN
Backlight brightness PWM input
104 In/Out SPD1
105 Out SPC1
Serial Port Data Input/Output for Chip BOOT ROM/EDID/HDCP
ROM
This pin functions as the bi-directional data pin of the serial port and operates
with inputs from 0 to 3.3V. Outputs are driven from 0 to 3.3V. This pin
requires an external 4k- 9 kpull up resistor to 3.3V.
Serial Port Clock Output for Chip BOOT ROM/EDID/HDCP ROM
209-1000-063 Rev 0.3
2013-1-25
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