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PDF TC58BVG0S3HBAI4 Data sheet ( Hoja de datos )

Número de pieza TC58BVG0S3HBAI4
Descripción 1 GBIT (128M x 8 BIT) CMOS NAND E2PROM
Fabricantes Toshiba 
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No Preview Available ! TC58BVG0S3HBAI4 Hoja de datos, Descripción, Manual

TC58BVG0S3HBAI4
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1 GBIT (128M × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58BVG0S3HBAI4 is a single 3.3V 1 Gbit (1,107,296,256 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 1024blocks.
The device has a 2112-byte static register which allows program and read data to be transferred between the
register and the memory cell array in 2112-bytes increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58BVG0S3HBAI4 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
The TC58BVG0S3HBAI4 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected
internally.
FEATURES
Organization
x8
Memory cell array 2112 × 64K × 8
Register
2112× 8
Page size
2112 bytes
Block size
(128K + 4K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
ECC Status Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 1004 blocks
Max 1024 blocks
Power supply
VCC = 2.7V to 3.6V
Access time
Cell array to register 40 µs typ.
Serial Read Cycle
25 ns min (CL=50pF)
Program/Erase time
Auto Page Program
Auto Block Erase
330 µs/page typ.
2.5 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
50 µA max
Package
P-TFBGA63-0911-0.80CZ (Weight: 0.15 g typ.)
8bit ECC for each 528Bytes is implemented on a chip.
1 2012-10-01C

1 page




TC58BVG0S3HBAI4 pdf
TC58BVG0S3HBAI4
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = -40 to 85 , VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
tCLS
CLE Setup Time
tCLH
CLE Hold Time
tCS CE Setup Time
tCH CE Hold Time
tWP Write Pulse Width
tALS
ALE Setup Time
tALH
ALE Hold Time
tDS Data Setup Time
tDH Data Hold Time
tWC Write Cycle Time
tWH WE High Hold Time
tWW
WP High to WE Low
tRR Ready to RE Falling Edge
tRW Ready to WE Falling Edge
tRP Read Pulse Width
tRC Read Cycle Time
tREA
RE Access Time
tCEA
CE Access Time
tCLR
CLE Low to RE Low
tAR ALE Low to RE Low
tRHOH
RE High to Output Hold Time
tRLOH
RE Low to Output Hold Time
tRHZ
RE High to Output High Impedance
tCHZ
CE High to Output High Impedance
tCSD
CE High to ALE or CLE Don’t Care
tREH
RE High Hold Time
tIR Output-High-impedance-to- RE Falling Edge
tRHW
RE High to WE Low
tWHC
WE High to CE Low
tWHR
WE High to RE Low
tWB WE High to Busy
tRST
Device Reset Time (Ready/Read/Program/Erase)
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns.
MIN MAX UNIT
12
5
20
5
12
12
5
12
5
25
10
100
20
20
12
25
20
25
10
10
25
5
60
20
0
10
0
30
30
60
100
5/5/10/500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
5 2012-10-01C

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TC58BVG0S3HBAI4 arduino
Read Cycle Timing Diagram
CLE
CE
tCLS tCLH
tCS tCH
tCLS tCLH
tCS tCH
TC58BVG0S3HBAI4
tCLR
WE
ALE
RE
I/O
RY / BY
tALH tALS
tALH tALS
tDS tDH
00h
tDS tDH tDS tDH tDS tDH tDS tDH
CA0 CA8 PA0 PA8
to 7 to 11 to 7 to 15
Col. Add. N
tR
tWB
tDS tDH
30h
tRC
tRR
70h
status
output
00h
tREA
DOUT DOUT
N N+1
Data out from
Col. Add. N
Read Cycle Timing Diagram: When Interrupted by CE
CLE
CE
tCLS
tCS
tCLH
tCH
tWC
WE
tALH tALS
tCLS
tCS
tCLH
tCH
tALH tALS
ALE
RE
I/O
RY / BY
tDS tDH
00h
tDS tDH tDS tDH tDS tDH tDS tDH
CA0 CA8 PA0 PA8
to 7 to 11 to 7 to 15
Col. Add. N
tR
tWB
tDS tDH
30h
tCLR
tCLR
tCSD
tRC tCHZ
tRR
70h
status
output 00h
tREA
tRHZ
tRHOH
DOUT DOUT
N N+1
Col. Add. N
11 2012-10-01C

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