PDF TH58NVG4S0FTAK0 Data sheet ( Hoja de datos )

Número de pieza	TH58NVG4S0FTAK0
Descripción	16 GBIT (2G x 8 BIT) CMOS NAND E2PROM
Fabricantes	Toshiba
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No Preview Available ! TH58NVG4S0FTAK0 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 16 GBIT (2G × 8 BIT) CMOS NAND E2PROM DESCRIPTION The TH58NVG4S0F is a single 3.3V 16 Gbit (18,152,947,712 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 232) bytes × 64 pages × 8192 blocks. The device has two 4328-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4328-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 14.5 Kbytes: 4328 bytes × 64 pages). The TH58NVG4S0F is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage. FEATURES • Organization x8 Memory cell array 4328 × 256K × 8 × 2 Register 4328 × 8 Page size 4328 bytes Block size (256K + 14.5K) bytes • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read • Mode control Serial input/output Command control • Number of valid blocks Min 8032 blocks Max 8192 blocks • Power supply VCC = 2.7V to 3.6V • Access time Cell array to register 30 µs max Serial Read Cycle 25 ns min (CL=100pF) • Program/Erase time Auto Page Program Auto Block Erase 300 µs/page typ. 3 ms/block typ. • Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby 30 mA max. 30 mA max 30 mA max 100 µA max • Package TSOP I 48-P-1220-0.50C • 4bit ECC for each 512Byte is required. 1 2011-07-01C 1 page TH58NVG4S0FTAK0 VALID BLOCKS SYMBOL PARAMETER MIN TYP. MAX UNIT NVB Number of Valid Blocks 8032  8192 Blocks NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. The first block (Block 0) is guaranteed to be a valid block at the time of shipment. The specification for the minimum number of valid blocks is applicable over lifetime The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 2.7  3.6 V VIH High Level input Voltage 2.7 V ≤ VCC ≤ 3.6 V Vcc x 0.8  VCC + 0.3 V VIL Low Level Input Voltage 2.7 V ≤ VCC ≤ 3.6 V −0.3*  Vcc x 0.2 * −2 V (pulse width lower than 20 ns) DC CHARACTERISTICS (Ta = -40 to 85℃, VCC = 2.7 to 3.6V) SYMBOL PARAMETER CONDITION IIL ILO ICCO0 1 ICCO1 2 ICCO2 2 ICCO3 2 ICCS Input Leakage Current Output Leakage Current Power On Reset Current Serial Read Current Programming Current Erasing Current Standby Current VIN = 0 V to VCC VOUT = 0 V to VCC PSL = GND or NU PSL = VCC, FFh command input after Power On CE = VIL, IOUT = 0 mA, tcycle = 25 ns   CE = VCC − 0.2 V, WP = 0 V/VCC, PSL = 0 V/VCC/NU MIN         TYP.         MAX ±10 ±10 30 30 30 30 30 100 V UNIT µA µA mA mA mA mA µA VOH High Level Output Voltage IOH = −0.4 mA 2.4   V VOL Low Level Output Voltage IOL = 2.1 mA   0.4 V IOL ( RY / BY ) Output current of RY / BY pin VOL = 0.4 V  1 Refer to application note (2) for detail 2 Icco1/2/3 are the value of one chip, and an unselected chip is in Standby mode. 8  mA 5 2011-07-01C 5 Page Read Cycle Timing Diagram CLE CE WE tCLS tCLH tCS tCH tWC tALH tALS TH58NVG4S0FTAK0 tCLS tCS tCLH tCH tCLR tALH tALS ALE RE I/O RY / BY tDS tDH 00h tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH CA0 CA8 PA0 PA8 PA16 to 7 to 12 to 7 to 15 to 17 Col. Add. N tR tWB tDS tDH 30h tRC tRR tCEA tREA DOUT DOUT N N+1 Data out from Col. Add. N Read Cycle Timing Diagram: When Interrupted by CE CLE CE tCLS tCS tCLH tCH tWC WE tALH tALS tCLS tCS tCLH tCH tALH tALS ALE RE I/O RY / BY tDS tDH 00h tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH CA0 CA8 PA0 PA8 PA16 to 7 to 12 to 7 to 15 to 17 Col. Add. N tR tWB tDS tDH 30h tCLR tCSD tRC tCHZ tRR tCEA tREA DOUT N tRHZ tRHOH DOUT N+1 Col. Add. N 11 2011-07-01C 11 Page

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