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PDF XC2VP30 Data sheet ( Hoja de datos )

Número de pieza XC2VP30
Descripción Virtex-II Pro and Virtex-II Pro X Platform FPGAs
Fabricantes Xilinx 
Logotipo Xilinx Logotipo



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No Preview Available ! XC2VP30 Hoja de datos, Descripción, Manual

Product Not Recommended For New Designs
1
R Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Complete Data Sheet
DS083 (v5.0) June 21, 2011
0
Product Specification
Module 1:
Introduction and Overview
10 pages
• Summary of Features
• General Description
• Architecture
• IP Core and Reference Support
• Device/Package Combinations and Maximum I/O
• Ordering Information
Module 2:
Functional Description
60 pages
• Functional Description: RocketIO™ X Multi-Gigabit
Transceiver
• Functional Description: RocketIO Multi-Gigabit
Transceiver
• Functional Description: Processor Block
• Functional Description: PowerPC™ 405 Core
• Functional Description: FPGA
- Input/Output Blocks (IOBs)
- Digitally Controlled Impedance (DCI)
- On-Chip Differential Termination
- Configurable Logic Blocks (CLBs)
- 3-State Buffers
- CLB/Slice Configurations
- 18-Kb Block SelectRAM™ Resources
- 18-Bit x 18-Bit Multipliers
- Global Clock Multiplexer Buffers
- Digital Clock Manager (DCM)
• Routing
• Configuration
Module 3:
DC and Switching Characteristics
59 pages
• Electrical Characteristics
• Performance Characteristics
• Switching Characteristics
• Pin-to-Pin Output Parameter Guidelines
• Pin-to-Pin Input Parameter Guidelines
• DCM Timing Parameters
• Source-Synchronous Switching Characteristics
Module 4:
Pinout Information
302 pages
• Pin Definitions
• Pinout Tables
- FG256/FGG256 Wire-Bond Fine-Pitch BGA Package
- FG456/FGG456 Wire-Bond Fine-Pitch BGA Package
- FG676/FGG676 Wire-Bond Fine-Pitch BGA Package
- FF672 Flip-Chip Fine-Pitch BGA Package
- FF896 Flip-Chip Fine-Pitch BGA Package
- FF1148 Flip-Chip Fine-Pitch BGA Package
- FF1152 Flip-Chip Fine-Pitch BGA Package
- FF1517 Flip-Chip Fine-Pitch BGA Package
- FF1696 Flip-Chip Fine-Pitch BGA Package
- FF1704 Flip-Chip Fine-Pitch BGA Package
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.
© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v5.0) June 21, 2011
Product Specification
www.xilinx.com
1

1 page




XC2VP30 pdf
Product Not Recommended For New Designs
R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Each RocketIO or RocketIO X core implements the following
technology:
• Serializer and deserializer (SERDES)
• Monolithic clock synthesis and clock recovery (CDR)
• 10 Gigabit Attachment Unit Interface (XAUI) Fibre
Channel (3.1875 Gb/s XAUI), Infiniband, PCI Express,
Aurora, SXI-5 (SFI-5,/SPI-5), and OC-48
compatibility(1)
• 8/16/32-bit (RocketIO) or 8/16/32/64-bit (RocketIO X)
selectable FPGA interface
• 8B/10B (RocketIO) or 8B/10B and 64B/66B
(RocketIO X) encoder and decoder with bypassing
option on each channel
• Channel bonding support (two to twenty channels)
- Elastic buffers for inter-chip deskewing and
channel-to-channel alignment
• Receiver clock recovery tolerance of up to
75 non-transitioning bits
• 50(RocketIO X) or 50/75selectable (RocketIO)
on-chip transmit and receive terminations
• Programmable comma detection and word alignment
• Rate matching via insertion/deletion characters
• Automatic lock-to-reference function
• Programmable pre-emphasis support
• Per-channel serial and parallel transmitter-to-receiver
internal loopback modes
• Optional transmit and receive data inversion
• Cyclic Redundancy Check support (RocketIO only)
PowerPC 405 Processor Block
The PPC405 RISC CPU can execute instructions at a sus-
tained rate of one instruction per cycle. On-chip instruction
and data cache reduce design complexity and improve sys-
tem throughput.
The PPC405 features include:
• PowerPC RISC CPU
- Implements the PowerPC User Instruction Set
Architecture (UISA) and extensions for embedded
applications
- Thirty-two 32-bit general purpose registers (GPRs)
- Static branch prediction
- Five-stage pipeline with single-cycle execution of
most instructions, including loads/stores
- Unaligned and aligned load/store support to cache,
main memory, and on-chip memory
- Hardware multiply/divide for faster integer
arithmetic (4-cycle multiply, 35-cycle divide)
- Enhanced string and multiple-word handling
- Big/little endian operation support
• Storage Control
- Separate instruction and data cache units, both
two-way set-associative and non-blocking
- Eight words (32 bytes) per cache line
- 16 KB array Instruction Cache Unit (ICU), 16 KB
array Data Cache Unit (DCU)
- Operand forwarding during instruction cache line fill
- Copy-back or write-through DCU strategy
- Doubleword instruction fetch from cache improves
branch latency
• Virtual mode memory management unit (MMU)
- Translation of the 4 GB logical address space into
physical addresses
- Software control of page replacement strategy
- Supports multiple simultaneous page sizes ranging
from 1 KB to 16 MB
• OCM controllers provide dedicated interfaces between
Block SelectRAM+ memory and processor block
instruction and data paths for high-speed access
• PowerPC timer facilities
- 64-bit time base
- Programmable interval timer (PIT)
- Fixed interval timer (FIT)
- Watchdog timer (WDT)
• Debug Support
- Internal debug mode
- External debug mode
- Debug Wait mode
- Real Time Trace debug mode
- Enhanced debug support with logical operators
- Instruction trace and trace-back support
- Forward or backward trace
• Two hardware interrupt levels support
• Advanced power management support
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
• Input block with an optional single data rate (SDR) or
double data rate (DDR) register
• Output block with an optional SDR or DDR register and
an optional 3-state buffer to be driven directly or
through an SDR or DDR register
• Bidirectional block (any combination of input and output
configurations)
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
• LVTTL, LVCMOS (3.3V,(2) 2.5V, 1.8V, and 1.5V)
• PCI-X compatible (133 MHz and 66 MHz) at 3.3V(3)
• PCI compliant (66 MHz and 33 MHz) at 3.3V(3)
• GTL and GTLP
1. Refer to Table 4, Module 2 for detailed information about RocketIO and RocketIO X transceiver compatible protocols.
2. Refer to XAPP659 for more information.
3. Refer to XAPP653 for more information.
DS083 (v5.0) June 21, 2011
Product Specification
www.xilinx.com
Module 1 of 4
4

5 Page





XC2VP30 arduino
Product Not Recommended For New Designs
R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Virtex-II Pro Data Sheet
The Virtex-II Pro Data Sheet contains the following modules:
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Introduction and Overview (Module 1)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Functional Description (Module 2)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC
and Switching Characteristics (Module 3)
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Pinout Information (Module 4)
DS083 (v5.0) June 21, 2011
Product Specification
www.xilinx.com
Module 1 of 4
10

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