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PDF TEA1753T Datasheet ( Hoja de datos )

Número de pieza TEA1753T
Descripción HV start-up DCM/QR flyback controller
Fabricantes NXP Semiconductors 
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TEA1753T datasheet

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TEA1753T pdf
NXP Semiconductors
6. Pinning information
6.1 Pinning
TEA1753T
HV start-up flyback controller with integrated PFC controller
VCC 1
GND 2
FBCTRL 3
FBAUX 4
LATCH 5
PFCCOMP 6
VINSENSE 7
PFCAUX 8
16 HV
15 HVS
14 PFCTIMER
TEA1753T
13 FBDRIVER
12 PFCDRIVER
11 PFCSENSE
10 FBSENSE
9 VOSENSE
001aan780
Fig 2. Pin configuration: TEA1753T (SOT109-1)
6.2 Pin description
Table 2. Pin description
Symbol
Pin
VCC
GND
1
2
FBCTRL
3
FBAUX
4
LATCH
5
PFCCOMP
6
VINSENSE
7
PFCAUX
8
VOSENSE
9
FBSENSE
10
PFCSENSE
11
PFCDRIVER 12
FBDRIVER
13
PFCTIMER
14
HVS
15
HV 16
Description
supply voltage
ground
flyback control input
auxiliary winding input for demagnetization timing and flyback OVP
general-purpose protection input
frequency compensation pin for PFC
mains voltage sense input
auxiliary winding input for demagnetization timing for PFC
sense input for PFC output voltage
flyback current sense input
PFC current sense input
PFC gate-driver output
flyback gate-driver output
delay timer pin for PFC on/off control
high-voltage safety spacer, not connected
high-voltage start-up / flyback valley sensing
TEA1753T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3. — 24 August 2012
© NXP B.V. 2012. All rights reserved.
5 of 32

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TEA1753T arduino
NXP Semiconductors
TEA1753T
HV start-up flyback controller with integrated PFC controller
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Fig 5. Soft-start-up of PFC
7.2.6 Low-power mode
When the output power of the flyback converter (see Section 7.3) is low, the flyback
converter switches over to frequency reduction mode. When the maximum switching
frequency of the flyback drops below 48 kHz, the power factor correction circuit is
switched off to maintain high efficiency. Connect a capacitor to the PFCTIMER pin to delay
switching off (see Section 7.2.7).
During low-power mode operation, the PFCCOMP pin is clamped to a minimum voltage of
3.5 V or 2.5 V and a maximum voltage of 3.9 V. The lower clamp voltage depends on the
voltage on VINSENSE pin. This voltage limits the maximum power that is delivered when
the PFC is switched on again. The upper clamp voltage ensures that the PFC returns from
low-power mode to its normal regulation point in a limited time.
When the flyback converter frequency exceeds 86 kHz, the power factor correction circuit
restores normal operation.
7.2.7
PFC off delay (PFCTIMER pin)
When the flyback converter maximum frequency drops below 48 kHz, the PFC is
switched off. The IC then outputs a 5 A current to the PFCTIMER pin. When the voltage
on the PFCTIMER pin reaches 3.6 V, the PFC is switched off by performing a soft-stop.
When the flyback converter frequency exceeds 86 kHz, a switch discharges the
PFCTIMER pin capacitor. When the voltage on the PCTIMER pin drops below 1.27 V, the
PFC is switched on (see Figure 6).
TEA1753T
Product data sheet
low power
5 µA
3.6 V
1.27 V
R
Q
low power delay
S (PFC on)
14 PFCTIMER
Fig 6. PFC start/stop via PPFCTIMER pin
All information provided in this document is subject to legal disclaimers.
Rev. 3. — 24 August 2012
014aaa740
© NXP B.V. 2012. All rights reserved.
11 of 32

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