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PDF 74HC165 Data sheet ( Hoja de datos )
| Número de pieza | 74HC165 | |
| Descripción | 8-bit parallel-in/serial out shift register | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 03 — 14 March 2008
Product data sheet
1. General description
The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with
JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with
complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
2. Features
I Asynchronous 8-bit parallel load
I Synchronous serial input
I Complies with JEDEC standard no. 7A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Applications
I Parallel-to-serial data conversion
1 page  
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
Fig 6. Timing diagram
inhibit
load
serial shift
mna993
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V
IOK
output clamping current
VO < −0.5 V or VO > VCC + 0.5 V
IO output current
−0.5 V < VO < VCC + 0.5 V
−0.5
[1] -
[1] -
-
+7
±20
±20
±25
V
mA
mA
mA
ICC
IGND
Tstg
supply current
ground current
storage temperature
- 50 mA
−50 -
mA
−65
+150
°C
74HC_HCT165_3
Product data sheet
Rev. 03 — 14 March 2008
© NXP B.V. 2008. All rights reserved.
5 of 22
5 Page 
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Table 7. Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
CPD power
per package;
[3] - 35 -
-
-
-
- pF
dissipation VI = GND to VCC − 1.5 V
capacitance
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
12. Waveforms
VI
CP or CE input
GND
VOH
Q7 or Q7 output
VOL
1/fmax
VM
tW
tPHL
VM
tTHL
tPLH
tTLH
mna987
Fig 7.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the output transition times
74HC_HCT165_3
Product data sheet
Rev. 03 — 14 March 2008
© NXP B.V. 2008. All rights reserved.
11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 74HC165.PDF ] | |
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