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PDF P8X32A-D40 Data sheet ( Hoja de datos )

Número de pieza P8X32A-D40
Descripción 8-Cog Multiprocessor Microcontroller
Fabricantes Parallax 
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PropellerP8X32A Datasheet
8-Cog Multiprocessor Microcontroller
1.0 PRODUCT OVERVIEW
1.1. Introduction
The Propeller chip is designed to provide high-speed processing for embedded systems while maintaining low current
consumption and a small physical footprint. In addition to being fast, the Propeller chip provides flexibility and power
through its eight processors, called cogs, that can perform simultaneous tasks independently or cooperatively, all while
maintaining a relatively simple architecture that is easy to learn and utilize. Two programming languages are available: Spin
(a high-level object-based language) and Propeller Assembly. Both include custom commands to easily manage the
Propeller chip’s unique features.
Figure 1: Propeller P8X32A Block Diagram
1.2. Stock Codes
Table 1: Propeller Chip Stock Codes
Device
Stock #
Package Type
I/O Power
Pins Requirements
External
Clock
Speed
Internal RC
Oscillator
Internal
Execution
Speed
P8X32A-D40
P8X32A-Q44
P8X32A-M44
40-pin DIP
44-pin LQFP
44-pin QFN
32
CMOS
3.3 volts DC
DC to 80
MHz
12 MHz or
20 kHz*
*Approximate; may range from 8 MHz – 20 MHz, or 13 kHz – 33 kHz, respectively.
0 to 160 MIPS
(20 MIPS/cog)
Global
ROM/RAM
64 K bytes;
32768 bytes
ROM / 32768
bytes RAM
Cog RAM
512 x 32 bits
per cog
Parallax, Propeller, Spin, and the Parallax and Propeller logos are trademarks of Parallax, Inc. All other trademarks are the property of their respective holders.
Copyright © Parallax Inc.
Page 1 of 37
Rev 1.2 4/24/2009

1 page




P8X32A-D40 pdf
Propeller™ P8X32A Datasheet
www.parallax.com
2.3. Typical Connection Diagrams
2.3.1. Propeller Clip or Propeller Plug Connection - Recommended
Note that the connections to the external oscillator and EEPROM, which are enclosed in dashed lines, are optional.
Propeller Clip, Stock #32200; Propeller Plug, Stock #32201. The Propeller Clip/Plug schematic is available for download
from www.parallax.com.
2.3.2. Alternative Serial Port Connection
Copyright © Parallax Inc.
Page 5 of 37
Rev 1.2 4/24/2009

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P8X32A-D40 arduino
Propeller™ P8X32A Datasheet
www.parallax.com
Table 6: Counter Modes (CTRMODE Field Values)
CTRMODE
Description
Accumulate
FRQx to PHSx
APIN
Output*
BPIN
Output*
%00000
Counter disabled (off)
0 (never)
0 (none)
0 (none)
%00001
%00010
%00011
PLL internal (video mode)
PLL single-ended
PLL differential
1 (always)
1
1
0
PLLx
PLLx
0
0
!PLLx
%00100
%00101
NCO single-ended
NCO differential
1
PHSx[31]
0
1
PHSx[31]
!PHSx[31]
%00110
%00111
%01000
%01001
%01010
%01011
%01100
%01101
%01110
%01111
DUTY single-ended
DUTY differential
POS detector
POS detector with feedback
POSEDGE detector
POSEDGE detector w/ feedback
NEG detector
NEG detector with feedback
NEGEDGE detector
NEGEDGE detector w/ feedback
1
1
A1
A1
A1 & !A2
A1 & !A2
!A1
!A1
!A1 & A2
!A1 & A2
PHSx-Carry
PHSx-Carry
0
0
0
0
0
0
0
0
0
!PHSx-Carry
0
!A1
0
!A1
0
!A1
0
!A1
%10000
%10001
%10010
%10011
%10100
%10101
%10110
%10111
%11000
%11001
%11010
%11011
%11100
%11101
%11110
LOGIC never
LOGIC !A & !B
LOGIC A & !B
LOGIC !B
LOGIC !A & B
LOGIC !A
LOGIC A <> B
LOGIC !A | !B
LOGIC A & B
LOGIC A == B
LOGIC A
LOGIC A | !B
LOGIC B
LOGIC !A | B
LOGIC A | B
0
!A1 & !B1
A1 & !B1
!B1
!A1 & B1
!A1
A1 <> B1
!A1 | !B1
A1 & B1
A1 == B1
A1
A1 | !B1
B1
!A1 | B1
A1 | B1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
%11111
LOGIC always
1 00
*Must set corresponding DIR bit to affect pin. A1 = APIN input delayed by 1 clock. A2 = APIN input delayed by 2 clocks. B1 = BPIN input delayed by 1 clock.
4.10. Video Generator
Each cog has a video generator module that facilitates
transmitting video image data at a constant rate. There are
two registers and one instruction which provide control
and access to the video generator. Counter A of the cog
must be running in a PLL mode and is used to generate
the timing signal for the Video Generator. The Video
Scale Register specifies the number of Counter A PLL
(PLLA) clock cycles for each pixel and number of clock
cycles before fetching another frame of data provided by
the WAITVID instruction which is executed within the cog.
The Video Configuration Register establishes the mode
the Video Generator should operate, and can generate
VGA or composite video (NTSC or PAL).
The Video Generator should be initialized by first starting
Counter A, setting the Video Scale Register, setting the
Video Configuration Register, then finally providing data
via the WAITVID instruction. Failure to properly initialize
the Video Generator by first starting PLLA will cause the
cog to indefinitely hang when the WAITVID instruction is
executed.
4.10.1. VCFG – Video Configuration Register
The Video Configuration Register contains the
configuration settings of the video generator and is shown
in Table 7.
In Propeller Assembly, the VMode through AuralSub
fields can conveniently be written using the MOVI
instruction, the VGroup field can be written with the MOVD
instruction, and the VPins field can be written with the
MOVS instruction.
Table 7: VCFG Register
31 30..29 28
27
26
25..23
22..12
11..9
8
-
VMode
CMode
Chroma1 Chroma0 AuralSub
-
VGroup
-
7..0
VPins
Copyright © Parallax Inc.
Page 11 of 37
Rev 1.2 4/24/2009

11 Page







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