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PDF FSTUD16450MTD Data sheet ( Hoja de datos )
| Número de pieza | FSTUD16450MTD | |
| Descripción | Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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January 2001
Revised August 2001
FSTUD16450
Configurable 4-Bit to 20-Bit Bus Switch with
-2V Undershoot Protection and Selectable Level Shifting
General Description
The Fairchild Universal Bus Switch FSTUD16450 provides
4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed CMOS
TTL-compatible bus switching. The low On Resistance of
the switch allows inputs to be connected to outputs without
adding propagation delay or generating additional ground
bounce noise.
The FSTUD16450 is designed to allow “customer” configu-
ration control of the enable connections. The device is
organized as either a 4-bit, 5-bit, 10-bit or 20-bit bus switch.
8-bit and 16-bit configurations are also achievable (see
Functional Description). The device's bit configuration is
chosen through select pin logic. (see Truth Table). When
OEx is LOW, Port Ax is connected to Port Bx. When OEx is
HIGH, the switch is OPEN.
The A and B Ports are “undershoot hardened” with UHC
protection to support an extended range to 2.0V below
ground. Fairchild's integrated “Undershoot Hardened
Circuit” (UHC) senses undershoot at the I/O's, and
responds by preventing voltage differentials from develop-
ing and turning on the switch.
Another key device feature is the addition of a level shifting
select pin, “S2”. When S2 is LOW, the device behaves as a
standard N-MOS switch. When S2 is HIGH, a diode to VCC
is integrated into the circuit allowing for level shifting
between 5V inputs and 3.3V outputs.
Features
s Undershoot hardened to −2V (A and B Ports)
s Voltage level shifting
s 4Ω switch connection between two ports
s Minimal propagation delay through the switch
s Low lCC
s Zero bounce in flow-through mode
s Control inputs compatible with TTL level
s See Applications Note AN-5008 for details
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Applications Note
Select pins S0, S1, S2 are intended to be used as static
user configurable control pins. The AC performance of
these pins has not been characterized or tested. Switching
of these select pins during system operation may tempo-
rarily disrupt output logic states and/or enable pin controls.
Ordering Code:
Order Number Package Number
Package Description
FSTUD16450GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
FSTUD16450MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1: BGA package available in Tape and Reel only.
UHC is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation DS500391
www.fairchildsemi.com
1 page  
Truth Tables (Continued)
Configuration 4
S0 = S1 = H
Inputs
OE1 OE2 OE3 OE4 OE5
LLLLL
L L L LH
L L LHL
L L LHH
L LHL L
L LHLH
L LHHL
L LHHH
LHL L L
LHLLH
LHLHL
LH LHH
LHHL L
L HH L H
L HHH L
L HHHH
HL L L L
HL L LH
HL LHL
H L LHH
HLHL L
HLHLH
H L HH L
H LHHH
HHL L L
HHL LH
HH L H L
HH LHH
HHHL L
HHH L H
HHHHL
HHHHH
1A1-4, 1B1-4
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
1Ax = 1Bx
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
4-Bit Configuration
Inputs/Outputs
1A5-8, 1B5-8
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
Z
Z
Z
Z
Z
Z
Z
Z
2A3-6, 2B3-6
2Ax = 2Bx
2Ax = 2Bx
2Ax = 2Bx
2Ax = 2Bx
Z
Z
Z
Z
2Ax = 2Bx
2Ax = 2Bx
2Ax = 2Bx
2Ax = 2Bx
Z
Z
Z
Z
2A7-10, 2B7-10
1A9-10, 2B9-10
2A1-2, 2B1-2
2Ay = 2By
2Ay = 2By
Z
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
2Ay = 2By
2Ay = 2By
Z
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
2Ay = 2By
2Ay = 2By
Z
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
2Ay = 2By
2Ay = 2By
Z
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
1Ay = 1By
Z
Z
Z
Z
Z
Z
Z
Z
2Ax = 2Bx
2Ax = 2Bx
2Ax = 2Bx
2Ax = 2Bx
Z
Z
Z
Z
2Ax = 2Bx
2Ax = 2Bx
2Ax = 2Bx
2Ax = 2Bx
Z
Z
Z
Z
2Ay = 2By
2Ay = 2By
Z
Z
2Ay = 2By
2Ay = 2By
Z
Z
2Ay = 2By
2Ay = 2By
Z
Z
2Ay = 2By
2Ay = 2By
Z
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
1Az = 1Bz
2Az = 2Bz
Z
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet FSTUD16450MTD.PDF ] | |
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