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PDF FSTUD16211 Data sheet ( Hoja de datos )

Número de pieza FSTUD16211
Descripción 24-Bit Bus Switch with -2V Undershoot Protection and Level Shifting
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FSTUD16211 Hoja de datos, Descripción, Manual

June 2000
Revised August 2001
FSTUD16211
24-Bit Bus Switch with 2V Undershoot Protection
and Level Shifting
General Description
The Fairchild Switch FSTUD16211 provides 24-bits of
high-speed CMOS TTL-compatible bus switching. The low
on resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. A diode to VCC has been
integrated into the circuit to allow for level shifting between
5V inputs and 3.3V outputs.
The device is organized as a 12-bit or 24-bit bus switch.
When OE1 is LOW, the switch is ON and Port 1A is con-
nected to Port 1B. When OE2 is LOW, Port 2A is connected
to Port 2B. When OE1/2 is HIGH, a high impedance state
exists between the A and B Ports. The A and B Ports have
“undershoot hardened” circuit protection to support an
extended range to 2.0V below ground. Fairchild’s inte-
grated Undershoot Hardened Circuit (UHC) senses
undershoot at the I/O’s, and responds by preventing volt-
age differentials from developing and turning on the switch.
Features
s Undershoot hardened to 2V (A and B Ports)
s Voltage level shifting
s 4switch connection between two ports
s Minimal propagation delay through the switch
s Low lCC
s Zero bounce in flow-through mode
s Control inputs compatible with TTL level
s See Applications Note AN-5008 for details
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number Package Number
Package Description
FSTUD16211GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
FSTUD16211MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Note 1: BGA package available in Tape and Reel only.
Logic Diagram
UHCis a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation DS500390
www.fairchildsemi.com

1 page




FSTUD16211 pdf
AC Loading and Waveforms
Note: Input driven by 50source terminated in 50
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 2. AC Test Circuit
FIGURE 3. AC Waveforms
5 www.fairchildsemi.com

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