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PDF CLAA141XD05 Data sheet ( Hoja de datos )
| Número de pieza | CLAA141XD05 | |
| Descripción | TFT LCD | |
| Fabricantes | CPT | |
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CPT
CHUNGHWA PICTURES TUBES, LTD.,
Chunghwa Picture Tubes, Ltd.
Technical Specification
To :
Date :
TFT LCD
CLAA141XD05
ACCEPTED BY :
Tentative
APPROVED BY
CHECKED BY
PREPARED BY
Prepared by : TFT-LCD Product Planning Management Division
CHUNGHWA PICTURE TUBES, LTD.
1127 Hopin Rd., Padeh, Taoyuan, Taiwan 334, R.O.C.
TEL: +886-3-3675151 FAX: +886-3-377-3001
Doc.No:
CLAA141XD05-V2-2004/05/21
CPT Confidential
0/19
Issue Date:
CLAA141XD05-Uniwill-V2-2004/07/21
1 page  
CPT
CHUNGHWA PICTURES TUBES, LTD.,
[Note 3]
LVDS Signal definition :
VIN+
100 Ω
VIN-
LVDS Receiver
VIN-
VCM
VCM+
VID
VID = VIN+ - VIN-
△VCM = | VCM+ - VCM- |
△VID = | VID+ - VID- |
VID+ = | VIH+ - VIH- |
VID- = | VIL+ - VIL- |
VCM = ( VIN+ - VIN- ) / 2
VCM+ = ( VIH+ - VIH- ) / 2
VCM- = ( VIL+ - VIL- ) / 2
VIN+
VIN+ = Positive differential DATA & CLK Input
VIN- = Negative differential DATA & CLK Input
VIH-
VIL-
VIH+
VIL+
(2) Backlight system
Ta = 25°C
ITEM
SYMBOL
MIN
TYP
MAX
UNIT
Lamp Voltage
VL - 680 -
V
Lamp Current
IL (3.0)
6.0
6.5 mA
Inverter Frequency
FI
-
52
- KHz
Lamp life time *1)
Life L
15,000
-
- hr
Starting Ta = 25℃
Lamp
Voltage*2) Tb = 0℃
Vs
-
-
- 900
V
- 1200
[Note 1]
*1) The time that module luminance reduced to 50% of initial value .
Base on Vs =(900) V , Ta = 25°C , IL=6.0 mA continuous.
Lamp Current measurement method ( The current meter is inserted in cold line)
LCD
Module
-A
+
Inverter
Power
Supply
*2) The lamp shall be stably lighted. Slide up method shall be used for
input voltage application. The voltage is applied voltage to both ends
of the lamp as the established starting voltage.
CPT Confidential
4/19 CLAA141XD05-Uniwill-V2-2004/07/21
5 Page 
CPT
CHUNGHWA PICTURES TUBES, LTD.,
(3)Timing Specifications
VCC=3.3V,Ta=25℃
ITEM
SYMBOL MIN TYP MAX UNIT
CLK frequency
fCLKin
-
65 66.6 MHz
CLK period
tCLKin 15.0
15.4
-
ns
LVDS High to Low transition time
LLHT - 0.75 1.5
LVDS Low to High transition time
LHLT - 0.75 1.5
LVDS
Input
Timing
Strobe position of Bit 0
Strobe position of Bit 1
Strobe position of Bit 2
Strobe position of Bit 3
Strobe position of Bit 4
f = 65MHz
Rspos0
Rspos1
Rspos2
Rspos3
Rspos4
0.7
2.9
5.1
7.3
9.5
1.1 1.4
3.3 3.6
5.5 5.8
7.7 8.0
9.9 10.2
Strobe position of Bit 5
Rspos5 11.7 12.1 12.4
Strobe position of Bit 6
Rspos6 13.9 14.3 14.6
RxIN Skew Margin
RSKM 400
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
Low width
tWDL
100
320
- tCLK
LCD input
signal
( LVDS
Tx Input ,
Rx output )
DENA
HD
VD
Horizontal Front Porch
Horizontal Back Porch
Vertical Front Porch
Vertical Back Porch
Frequency
Period
Low width
Frequency
Period
Low width
tHFP
tHBP
tVFP
tVBP
fH
tH
tWHL
fV
tV
tWVL
0
4
2
1
-
1100
1
-
772
1
24
296
3
35
48.5
1344
136
60
806
6
- tCLK
- tCLK
- tH
- tH
55.9 kHz
- tCLK
- tCLK
62 Hz
- tH
- tH
[Note]
1) Polarities of HD and VD are negative in this specification.
2) DENA (Data Enable) should always be positive polarity as shown in the timing
specification.
3) CLKIN should appear during all invalid period, and HD should appear during invalid
period of frame cycle.
4) LVDS Receiver is DS90C384A(NS made) or function identical to DS90C384A.
CPT Confidential
10/19
CLAA141XD05-Uniwill-V2-2004/07/21
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CLAA141XD05.PDF ] | |
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