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PDF CL5767 Data sheet ( Hoja de datos )

Número de pieza CL5767
Descripción single-chip FM stereo radio
Fabricantes Comlent Technology 
Logotipo Comlent Technology Logotipo



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No Preview Available ! CL5767 Hoja de datos, Descripción, Manual

CL5 767
Doc. Version
Comlent Technology Inc.
1.0
ProductCL5767
Date
2009-01-20
Page #: 23
CL5767 Datasheet
(For Strategic Customers)
1

1 page




CL5767 pdf
CL5 767
(IIP3OUTBAND)
AM Suppression(AMSP)
fTUNE =76~108MHz
VRF=60dBuV
FMfDEV=22.5kHz; fMOD=1kHz;
AMm=0.3; fMOD=1kHz;
BAF=200Hz ~15kHz;MONO=ON
50
Adjacent Channel Selectivity
(ACS200)
Alternate Channel Selectivity
(ACS400)
Δf=±200kHz; fTUNE =76~108MHz
SINAD>26dB
Δf=±400kHz; fTUNE =76~108MHz
SINAD>26dB
40
45
Spurious Response
Rejection
Audio Output Voltage
Audio Output L/R Imbalance
Audio Stereo Separation
Signal to Noise and
Distortion Ratio(SINAD)
Audio THD
De-emphasis Time Constant
Seek Time
Power-up Time
Δf>±1MHzfTUNE =76~108MHz
SINAD>26dB
VRF=60dBuV;
fTUNE=76~108MHz fDEV =22.5kHz;
fMOD =1kHz; BAF=200Hz ~15kHz;
MONO=ON; MAX. Volume
VRF=60dBuV;
fTUNE=76~108MHz;fDEV =22.5kHz;
fMOD=1kHz;BAF=200Hz ~15kHz;
VRF=60dBuV;
fTUNE = 76~108MHz; fDEV =100%;
fMOD=1kHz; L=1;R=0; Pilot 10%
BAF=200Hz ~15kHz;
VRF=60dBuV;
fTUNE = 76~108MHz; fDEV =75kHz;
fMOD =1kHz; BAF=200Hz ~15kHz;
MONO=ON
VRF=60dBuV;
fTUNE = 76~108MHz; fDEV =75kHz;
fMOD =1kHz; BAF=200Hz ~15kHz;
MONO=ON
DE=0
DE=1
60
29
53
80
0.1
32
55
0.07
75
50
50
33
58
0.1
1
External Reference Clock ModeIn Addition to 32.768kHz Crystal Mode
Reference Clock Frequency
Jitter
Support Two Clock Frequency
For Audio SNR > 40dB
32.768kHz or 13MHz
1
Confidential and Proprietary
EMF
dB
dB
dB
dB
mV RMS
dB
dB
dB
%
us
ms/C
s
ns
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CL5767 arduino
CL5 767
4.5 Tuning and Seeking under P-Mode
Tuning under P-Mode is triggered by changing control bit PLL[13:0]. If the chip read the same
PLL[13:0] number, it will keep current working status and there is no PLL locking process, if the chip
read in a different PLL[13:0] number, PLL relocks and the chip is tuned to new frequency. When
tuning is completed, it provides two control bits: 7-bit IF and 4-bit Lev. The suggested criteria of radio
station are(48IF62)&(Lev5).
Seeking function under P-Mode is triggered by control bit SM rising edge, i.e. SM from 0 to 1. When
seeking is completed, it sends out two control bits: RF and BLF. RF = 1 means that seeking is
completed, if BLF =0, there is a radio station, if BLF=1, there is no radio station across FM band.
Radio station frequency can be acquired from control bit PLL[13:0] in read-only registers.
4.6 Reference Clock
The CL5767 can be used with 32.768 kHz crystal, the required frequency stability is less than +/-
50ppm in the working temperature range. Also it accepts a 32.768 kHz or 13MHz reference clock,
the required jitter is less than 1ns.
4.7 Control Interface
Two-wire slave-transceiver (I2C interface) is provided for the controller IC to read and write the
control registers. Registers may be written and read when the VIO supply is applied regardless of
the state of the VBAT supplies.
For two-wire operation, a transfer begins with the START condition. The control word is latched
internally on rising SCLK edges. The device acknowledges the address by setting SDIO low on the
next falling SCLK edge.
For write operations, the device acknowledge is followed by an eight bit data word latched internally
on rising edges of SCLK. The device always acknowledges the data by setting SDIO low on the next
falling SCLK edge.
For read operations, the device acknowledge is followed by an eight bit data word shifted out on
falling SCLK edges. The controller IC returns an acknowledge if additional data will be transferred.
The transfer ends with the STOP conditions regardless of the state of the acknowledge.
Confidential and Proprietary
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