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PDF FSTD32450GX Data sheet ( Hoja de datos )
| Número de pieza | FSTD32450GX | |
| Descripción | Configurable 4-Bit to 40-Bit Bus Switch with Selectable Level Shifting (Preliminary) | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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Preliminary
February 2001
Revised August 2001
FSTD32450
Configurable 4-Bit to 40-Bit Bus Switch with
Selectable Level Shifting (Preliminary)
General Description
The Fairchild Universal Bus Switch FSTD32450 provides
4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed
CMOS TTL-compatible bus switching. The low On Resis-
tance of the switch allows inputs to be connected to out-
puts without adding propagation delay or generating
additional ground bounce noise.
The FSTD32450 is designed to allow “customer” configura-
tion control of the enable connections. The device can be
organized as either a ten 4-bit, eight 5-bit, four 10-bit, two
20-bit or one 40-bit enabled bus switch. Also achievable
are 8-bit and 16-bit enabled configurations (see Functional
Description). The device’s bit configuration is controlled
through select pin logic. (see Truth Table). When OEx is
LOW, Port Ax is connected to Port Bx. When OEx is HIGH,
the switch is OPEN.
Another key device feature is the addition of a level shifting
select pin, “S2 and S5”. When S2 and S5 are LOW, the
device behaves as a standard N-MOS switch. When S2
and S5 are HIGH, a diode to VCC is integrated into the cir-
cuit allowing for level shifting between 5V inputs and 3.3V
outputs.
Features
s Voltage level shifting
s 4Ω switch connection between two ports
s Minimal propagation delay through the switch
s Low lCC
s Zero bounce in flow-through mode
s Control inputs compatible with TTL level
s Packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Applications Note
Select pins S0, S1, S2, S3, S4 and S5 are intended to be
used as static user configurable control pins. The AC per-
formance of these pins has not been characterized or
tested. Switching of these select pins during system opera-
tion may temporarily disrupt output logic states and/or
enable pin controls.
40-bit configuration can be achieved by connecting the
OE1 and the OE6 pins to together.
Ordering Code:
Order Number Package Number
Package Description
FSTD32450GX
(Note 1)
BGA114A
(Preliminary)
114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
Note 1: BGA package available in Tape and Reel only.
UHC is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation DS500563
www.fairchildsemi.com
1 page  
Preliminary
Functional Description
The device can also be configured as an 8 and 16-bit device by grounding the unused pins in Configurations 2 and 1
respectively. The 8-bit configuration may also be achieved by tying two of the 4-bit enables from configuration together and
tying the remaining enable pin (OE) HIGH.
Truth Tables (X = VCC or GND)
(see Functional Description)
S2, S5
L
H
Select Pin
Mode
Std. NMOS Switch
Level Shifting Diode Enabled
20-Bit Configuration (S0 = S1 = L)
Inputs
OE1
OE2
OE3
LXX
HXX
OE6
L
H
Inputs
OE7
X
OE8
X
XX
OE4
X
X
S3 = S4 = L
OE9
X
X
OE5
X
X
OE10
X
X
Inputs/Outputs
1A1-10 = 1B1-10, 2A1-10 = 2B1-10
Z
Inputs/Outputs
3A1-10 = 3B1-10, 4A1-10 = 4B1-10
Z
10-Bit Configuration (S0 = L, S1 = H)
Inputs
OE1
OE2
OE3
OE4
LXXL
L XXH
HXX L
HXXH
S3 = L, S4 = H
Inputs
OE6
L
OE7
X
OE8
X
OE9
L
L XXH
HXX L
HXXH
OE5
X
X
X
X
OE10
X
X
X
X
Inputs/Outputs
1A1-10 = 1B1-10
1AX = 1BX
1AX = 1BX
Z
Z
2A1-10 = 2B1-10
2AX = 2BX
Z
2AX = 2BX
Z
Inputs/Outputs
4A1-10 = 4B1-10
4AX = 4BX
4AX = 4BX
Z
Z
3A1-10 = 3B1-10
3AX = 3BX
Z
3AX = 3BX
Z
5 www.fairchildsemi.com
5 Page 
AC Loading and Waveforms
Preliminary
Note: Input driven by 50Ω source terminated in 50Ω
Note: CL includes load and stray capacitance
Note: Input Frequency = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet FSTD32450GX.PDF ] | |
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