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PDF ADV7481 Data sheet ( Hoja de datos )

Número de pieza ADV7481
Descripción Integrated Video Decoder and Dual Mode HDMI/MHL Receiver
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
Integrated Video Decoder and
Dual Mode HDMI/MHL Receiver
ADV7481
FEATURES
Analog input
Worldwide NTSC/PAL/SECAM color demodulation support
with autodetection
One 10-bit ADC, 4× oversampling for CVBS, Y/C, and YPbPr
8 analog video input channels with on-chip antialiasing filter
Fully differential, pseudo differential, and single-ended
CVBS video input support
STB diagnostics on differential video inputs
CVBS (composite), Y/C (S-Video), and YPbPr (component)
video input support
Fast switching capability between analog inputs
Adaptive contrast enhancement (ACE)
Excellent common-mode noise rejection capabilities
Rovi (Macrovision) copy protection detection
Up to 4 V common-mode input range solution
Vertical blanking interval (VBI) data slicer
Mobile High-Definition Link (MHL) capable receiver
High-bandwidth Digital Content Protection (HDCP)
authentication and decryption support
75 MHz maximum pixel clock frequency, allowing HDTV
formats up to 720p/1080i at 60 Hz
24 bits per pixel mode supported
HDCP repeater support, up to 25 KSVs supported
Adaptive TMDS equalizer
High-Definition Multimedia Interface (HDMI) capable
receiver
HDCP authentication and decryption support
162 MHz maximum pixel clock frequency, allowing HDTV
formats up to 1080p and display resolutions up to UXGA
(1600 × 1200 at 60 Hz)
HDCP repeater support, up to 25 KSVs supported
Integrated CEC controller, CEC 1.4 compatible
Adaptive TMDS equalizer
5 V detect and Hot Plug assert
Component video processor
Any-to-any 3 × 3 color space conversion (CSC) matrix
Contrast/brightness/hue/saturation video adjustment
Timing adjustments controls for horizontal sync
(HS)/vertical sync (VS)/data enable (DE) timing
Video mute function
Serial digital audio output interface
HDMI/MHL audio extraction support
Advanced audio muting feature
I2S-compatible, left justified, and right justified audio
output modes
8-channel TDM output mode available
2 Mobile Industry Processor Interface (MIPI) Camera Serial
Interface 2 (CSI-2) transmitters
4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing
options for HDMI/MHL/SDP/digital input port sources
1-lane transmitter for standard definition processor (SDP)
sources
8-bit digital input/output port
General
2-wire serial microprocessor unit (MPU) interface (I2C
compatible)
−40°C to +85°C temperature grade
100-ball, 9 mm × 9 mm, RoHS-compliant CSP_BGA package
Qualified for automotive applications
APPLICATIONS
Portable devices
Automotive infotainment (head unit and rear seat
entertainment systems)
HDMI repeaters and video switches
FUNCTIONAL BLOCK DIAGRAM
RXCP/RXCN
RX0P/RX0N
RX1P/RX1N
RX2P/RX2N
DDC_SCL/
CD_PULLU P
DDC_SD A
HPD/CBUS
CD_SENSE
CEC
RX_5V/VBUS
VBUS_EN
LLC
P0 TO P7
AIN1 TO
AIN8
DIAG1 TO
DIAG4
MHL_SENSE
CBUS
DDC
HDMI/MHL
RECEIVER
CEC
HPD
EDID RAM
HDCP
8-BIT TTL
INPUT/OUTPUT
ADV7481
AUDIO
PROCESSOR
CP
CORE
AFE
SD
CORE
DIAGNOSTIC
SPI SLAVE
I2C SLAVE
INTERRUPTS
CONTROLLER
AUDIO OUTPUT
FORMATTER
4-LANE
MIPI CSI-2
TRANSMITTER
1-LANE
MIPI CSI-2
TRANSMITTER
SPI_MISO
SPI_MOSI
SPI_SCLK
SPI_CS
ALSB
SCLK
SDATA
INTRQ1 TO
INTRQ3
I2S_MCLK
I2S_LRCLK
I2S_SCLK
I2S_SDATA
CLKAP/CLKAN
DA0P/DA0N TO
DA3P/DA3N
CLKBP/CLKBN
DB0P/DB0N
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




ADV7481 pdf
Data Sheet
ADV7481
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,
DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS1
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance2
CRYSTAL INPUT
Input High Voltage
Input Low Voltage
DIGITAL OUTPUTS1
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance2
POWER REQUIREMENTS
Digital Power Supply
HDMI/MHL Terminator Supply
HDMI/MHL Comparator Supply
PLL Power Supply
MIPI Transmitters Power Supply
Digital Input/Output Power Supply1
Analog Power Supply
CURRENT CONSUMPTION1, 2, 3, 4
Digital Supply Current
Single-Ended CVBS Input
Fully Differential and Pseudo
Differential CVBS Input
Y/C Input
YPbPr Input
HDMI Input
MHL Input
8-Bit Digital Input
Symbol Test Conditions/Comments
N
INL CVBS mode
DNL CVBS mode
SCLK, SDATA, RESET, ALSB, SPI_CS, SPI_SCLK,
SPI_MOSI, LLC, and P0 to P7
VIH DVDDIO = 3.14 V to 3.46 V
VIL DVDDIO = 3.14 V to 3.46 V
IIN
CIN
VIH XTALP
VIL XTALP
LLC, P0 to P7, I2S_MCLK, I2S_SCLK, I2S_LRCLK,
I2S_SDATA, SPI_MISO, SDATA, INTRQ1 to INTRQ3
(when configured to drive when active), and
VBUS_EN
VOH DVDDIO = 3.14 V to 3.46 V and ISOURCE = 0.4 mA
VOL DVDDIO = 3.14 V to 3.46 V and ISINK = 3.2 mA
ILEAK
COUT
DVDD
TVDD
CVDD
PVDD
MVDD
DVDDIO
AVDD
3.3 V operation
IDVDD
Min Typ Max Unit
10
2
±0.6
Bits
LSB
LSB
2V
0.8 V
−10 +10 µA
10 pF
1.2 V
0.4 V
2.4
10
V
0.4 V
µA
20 pF
1.71 1.8
3.14 3.3
1.71 1.8
1.71 1.8
1.71 1.8
3.14 3.3
1.71 1.8
1.89 V
3.46 V
1.89 V
1.89 V
1.89 V
3.46 V
1.89 V
279
74.5
74.7
71.3
72.8
68.1
93.5
32.5
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0 | Page 5 of 22

5 Page





ADV7481 arduino
Data Sheet
Timing Diagrams
SDATA
SCLK
t3 t5
t6
t2
t1
t7
Figure 3. I2C Timing
t3
t4
t8
SPI
MODE CPOL CPHA
SPI_CS
0 0 0 SPI_SCLK
1 0 1 SPI_SCLK
2 1 0 SPI_SCLK
3 1 1 SPI_SCLK
SPI_MO SI
t9
W/R
DEVICE ADDRESS
SUB ADDRESS
DATA IN 0
DATA IN 1
76 5 43 2 10 7 6 5 43 2 107 6 5 43 2 107 6 5 43 2 10
DELAY MODE 1
SPI_MI SO
DELAY MODE 0
SPI_MI SO
SPI_SCLK
DUMMY BYTE
DATA OUT 0
76543210
DATA OUT 0
DATA OUT 1
7654321076543210
Figure 4. Detailed SPI Slave Timing Diagram
t12
t13 t14
t16
t15
SPI_MOSI
SPI_CS
SPI_MISO
Figure 5. SPI Slave Mode Timing (SPI Mode 0 and SPI Mode 3)
SPI_SCLK
t12
t17
t18
t20
t19
SPI_MO SI
SPI_CS
SPI_MISO
Figure 6. SPI Slave Mode Timing (SPI Mode 1 and SPI Mode 2)
ADV7481
t11
t10
Rev. 0 | Page 11 of 22

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