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PDF IR35211 Data sheet ( Hoja de datos )
| Número de pieza | IR35211 | |
| Descripción | Dual Output Digital Multi-Phase Controller | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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Dual Output Digital Multi-Phase Controller IR35211
FEATURES
Dual output 3+1 phase PWM Controller
Easiest layout and fewest pins in the industry
Fully supports AMD® SVI1 & SVI2 with dual
OCP and Intel® VR12 & VR12.5
Overclocking & Gaming Mode
Switching frequency from 200kHz to 2MHz
per phase
IR Efficiency Shaping Features including
Dynamic Phase Control and Automatic Power
State Switching
Programmable 1-phase operation for Light
Loads and Active Diode Emulation for Very
Light Loads
IR Adaptive Transient Algorithm (ATA) on
both loops minimizes output bulk capacitors
and system cost
Auto-Phase Detection with auto-
compensation
Per-Loop Fault Protection: OVP, UVP, OCP,
OTP
I2C/SMBus/PMBus system interface for
telemetry of Temperature, Voltage, Current &
Power for both loops
Multiple Time Programming (MTP) with
integrated charge pump for easy custom
configuration
Compatible with IR ATL and 3.3V tri-state
Drivers
+3.3V supply voltage; -40°C to 85°C ambient
operation
Pb-Free, Halogen Free, RoHS, 6x6mm,
40-pin, 0.5 mm pitch QFN
DESCRIPTION
The IR35211 is a dual loop digital multi-phase buck
controller designed for CPU voltage regulation and is fully
compliant to AMD® SVI1 & SVI2 Rev 1.2 & Intel© VR12
Rev 1.5 PWM specification and VR12.5 Rev 1.3 PWM
specification.
The IR35211 includes IR’s Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. IR’s Dynamic Phase
Control adds/drops active phases based upon load
current and can be configured to enter 1-phase operation
and diode emulation mode automatically or by command.
IR’s unique Adaptive Transient Algorithm (ATA), based
on proprietary non-linear digital PWM algorithms,
minimizes output bulk capacitors and Multiple Time
Programmable (MTP) storage saves pins and enables a
small package size. Device configuration and fault
parameters are easily defined using the IR Digital Power
Design Center (DPDC) GUI and stored in on-chip MTP.
The IR35211 provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based
temperature sensing with VRHOT signal.
The IR35211 includes numerous features like register
diagnostics for fast design cycles and platform
differentiation, simplifying VRD design and enabling
fastest time-to-market (TTM) with “set-and-forget”
methodology.
APPLICATIONS
AMD® SVI1 & SVI2, Intel® VR12 & VR12.5 based
systems
Desktop & Notebook CPU VRs
High Performance Graphics Processors
ORDERING INFORMATION
Base Part
Number
IR35211
Package Type
QFN 6 mm x 6 mm
Standard Pack
Form
Quantity
Tape and Reel
3000
Orderable
Part Number
IR35211MxxyyTRP1
IR35211
QFN 6 mm x 6 mm
Tape and Reel
3000
IR35211MTRPBF
IR35211
QFN 6 mm x 6 mm
Tray
4900
IR35211MTYPBF
Notes 1: Customer Specific Configuration File, where xx = Customer ID and yy = Configuration File (Codes assigned by IR Marketing).
1 www.irf.com | © 2014 International Rectifier
July 24, 2014 | V1.00
1 page  
Dual Output Digital Multi-Phase Controller IR35211
PIN DESCRIPTIONS
PIN#
PIN NAME
TYPE
PIN DESCRIPTION
1
RCSP
A [O]
Resistor Current Sense Positive Loop#1. This pin is connected to an external network to set
the load line slope, bandwidth and temperature compensation for Loop #1.
2
RCSM
A [O]
Resistor Current Sense Minus Loop#1. This pin is connected to an external network to set the
load line slope, bandwidth and temperature compensation for Loop #1.
Voltage Regulator Ready Output (Loop #2). Open-drain output that asserts high when the VR
3
VRDY2
D [O] has completed soft-start to Loop #2 boot voltage. It is pulled up to an external voltage rail through
and external resistor.
4
VSEN
A [I]
Voltage Sense Input Loop#1. This pin is connected directly to the VR output voltage of Loop #1
at the load and should be routed differentially with VRTN.
5
VRTN
A [I]
Voltage Sense Return Input Loop#1. This pin is connected directly to Loop#1 ground at the
load and should be routed differentially with VSEN.
6
RRES
A [B]
Current Reference Resistor. A 1% 7.5kohm resistor is connected to this pin to set an internal
precision current reference.
7
TSEN1
A [I]
NTC Temperature Sense Input Loop #1. An NTC network is connected to this pin to measure
temperature for VRHOT. Refer to page 44 for details.
8
V18A
A [O] 1.8V Decoupling. A capacitor on this pin provides decoupling for the internal 1.8V supply.
Voltage Regulator Ready Output (Loop #1). Open-drain output that asserts high when the VR
9
VRDY1
D [O] has completed soft-start to Loop #1 boot voltage. It is pulled up to an external voltage rail through
and external resistor.
Power OK Input (AMD). An input that when low indicates to return to the Boot voltage and when
high indicates to use the SVI bus to set the the output voltage.
PWROK/
VR Enable for Loop 2. When configured, ENABLE for Loop 2 is an active high system input to
10
EN_L2/
D [I]
power-on Loop 2, provided Vin and Vcc are present. ENABLE is not pulled up on the controller.
When ENABLE is pulled low, the controller de-asserts VR READY2 and shuts down loop 2 only.
INMODE
Intel Mode Pin. If configured this pin will select whether the controller is in VR12 or VR12.5
Mode. If pulled low (Logic 0) the controller will operate in VR12.5 mode, if pulled high (Logic 1)
the controller will operate in VR12 mode.
11
VINSEN
A [I]
Voltage Sense Input. This is used to detect and measure a valid input supply voltage (typically
5V-19V) to the VR. Refer to page 16 for details.
VDDIO Input (AMD). This pin provides the voltage to which the SVT line and the SVD
12
VDDIO/
SV_ADDR
A [P]/ Acknowledge are driven high.
D [I] SVID Address Input (INTEL). A resistor to ground on this pin defines the SVID address which is
latched when Vcc becomes valid. Requires a 0.01µF bypass capacitors to GND.
13
SVT/
SV_ALERT#
D [O]
SVI Telemetry Output (AMD). Telemetry and VOTF information output by the IR35211.
Serial VID ALERT# (INTEL). SVID ALERT# is pulled low by the controller to alert the CPU of
new VR12/12.5 Status.
14
SV_CLK/
VIDSEL1
Serial VID Clock Input. Clock input driven by the CPU Master.
D [I] Parallel VID Selection. When configured in GPU parallel VID mode, this is pin is used to select
the VID voltage registers.
Serial VID Data I/O. Is a bi-directional serial line over which the CPU Master issues commands
15
SV_DIO/
VIDSEL0
D [B]/ to controller/s slave/s.
D [I] Parallel VID Selection. When configured in GPU parallel VID mode, this is pin is used to select
the VID voltage registers.
16
VRHOT_ICRIT#
D [O]
VRHOT_ICRIT# Output. Active low alert pin that can be programmed to assert if temperature or
average load current exceeds user-definable thresholds.
VR Enable Input. ENABLE is an active high system input to power-on the regulator, provided Vin
17 EN D [I] and Vcc are present. ENABLE is not pulled up on the controller. When ENABLE is pulled low, the
controller de-asserts VR READY and shuts down the regulator.
Bus Address & I2C Bus Protection. A resistor to ground on this pin defines the I2C address
18 ADDR_PROT D [B] offset which is latched when Vcc becomes valid. Subsequently, this pin becomes a logic input to
enable or disable communication on the I2C bus offset when protection is enabled.
19
SM_DIO
D [B] Serial Data Line I/O. I2C/SMBus/PMBus bi-directional serial data line.
5 www.irf.com | © 2014 International Rectifier
July 24, 2014 | V1.00
5 Page 
Dual Output Digital Multi-Phase Controller IR35211
PARAMETER
Fault Protection
OVP Threshold During Start-up
(until output reaches 1V)
OVP Operating Threshold1
(programmable)
Output UVP Threshold1 (programmable)
OVP/UVP Filter Delay1
Fast OCP Range (per phase)1
Fast OCP Filter Bandwidth1
Slow OCP Filter Bandwidth1
OCP System Accuracy1
VR_HOT Range1
OTP Range1
Dynamic Phase Control
Current Filter Bandwidth1
Timing Information
Automatic Configuration from MTP1
Automatic Trim Time1
EN Delay (to ramp start) 1
VID Delay (to ramp start) 1
VRDY1/2 Delay1
SYMBOL
t3-t2
t4-t3
CONDITIONS
MIN TYP MAX UNIT
Relative to VID
Relative to VID
System excluding
DCR/sense resistor
VR_HOT level + OTP
Range
1.2 1.275 1.35 V
-
150 to
500
-
mV
-
-150 to -
500
-
mV
- 160 - ns
-
0 to 62
-
A
- 60 - kHz
- 3.2/52 - Hz
- ±2 - %
-
64 to 127
-
°C
-
64 to 134
-
°C
For Phase drop
- 5.3 - kHz
3.3V ready to end of
configuration
Loop bandwidth dependent
After reaching Boot voltage
-
-
-
-
-
- 1 ms
- 4 ms
3 - µs
5 - µs
20 - µs
Notes:
1 Guaranteed by design.
2 PWM operating frequency will vary slightly as the number of phases changes (increases/decreases) because of the internal calculation
involved in dividing a switching period evenly into the number of active phases.
3 System accuracy is for a temperature range of 0°C to +85°C. Accuracies will derate by a factor of 1.5x for temperatures outside the 0°C to
+85°C range.
11 www.irf.com | © 2014 International Rectifier
July 24, 2014 | V1.00
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IR35211.PDF ] | |
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