PDF LH79524 Data sheet ( Hoja de datos )

Número de pieza	LH79524
Descripción	System-on-Chip
Fabricantes	NXP Semiconductors
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Preliminary data sheet LH79524/LH79525 (A.1) System-on-Chip FEATURES • Highly Integrated System-on-Chip • High Performance: 76.205 MHz CPU Speed, 50.803 MHz maximum AHB clock (HCLK) • 32-bit ARM720T™ RISC Core – LH79524: 32-bit External Data Bus – 208 LFBGA package – LH79525: 16-bit External Data Bus – 176 LQFP package • 8 kB Cache with Write Back Buffer • MMU (Windows CE™ Enabled) • 16 kB On-Chip SRAM • Flexible, Programmable Memory Interface – SDRAM Interface – 512 MB External Address Space – 32-bit External Data Bus (LH79524) – 16-bit External Data Bus (LH79525) – SRAM/Flash/ROM Interface – 15-bit External Address Bus – 32-bit External Data Bus (LH79524) – 16-bit External Data Bus (LH79525) • Multi-stream DMA Controller – Four 32-bit Burst-Based Data Streams • Clock and Power Management – 32.768 kHz Oscillator for Real Time Clock – 10 MHz to 20 MHz Oscillator and On-chip PLL – Active, Standby, Sleep, Stop1, and Stop2 Modes – Externally-supplied Clock Options • On-Chip Boot ROM – Allows Booting from 8-, 16-, or 32-bit Devices – NAND Flash Boot • Low Power Modes – Active Mode: 85 mA (MAX.) – Standby Mode: 50 mA (MAX.) – Sleep Mode: 3.8 mA (TYP.) – Stop Mode 1: 420 µA (TYP.) – Stop Mode 2: 25 µA (TYP.) • USB Device – Compliant with USB 2.0 Specifications (Full Speed) – Four Endpoints • Ethernet MAC, with MII and MDIO Interfaces – IEEE 802.3 Compliant – 10 and 100 Mbit/s Operation • Analog-to-Digital Converter/Brownout Detector – 10-bit ADC – Pen Sense Interrupt – Integrated Touch Screen Controller (TSC) Preliminary data sheet • I2C Module • Integrated Codec Interface Support Features (I2S) • Watchdog Timer • Vectored Interrupt Controller – 16 Standard and 16 Vectored IRQ Interrupts – Interrupts Individually Configurable as IRQ or FIQ • Three UARTs – 16-entry FIFOs for Rx and Tx – IrDA SIR Support on all UARTs • Three 16-bit Timers with PWM capability • Real Time Clock – 32-bit Up-counter with Programmable Load – Programmable 32-bit Match Compare Register • Programmable General Purpose I/O Signals – LH79524: 108 available pins on 14 ports – LH79525: 86 available pins on 12 ports • Programmable Color LCD Controller – 16 (LH79524) or 12 (LH79525) Bits-per-Pixel – Up to 800 × 600 resolution – STN, Color STN, HR-TFT, AD-TFT, TFT – TFT: Supports 64 k (LH79524) or 4 k (LH79525) Direct Colors or 256 colors selected from a Palette of 64 k Colors; 15 Shades of Gray – Color STN: Supports 3,375 Direct Colors or 256 Colors Selected from a Palette of 3,375 Colors • Synchronous Serial Port – Supports Data Rates Up to 1.8452 Mbit/s – Compatible with Common Interface Schemes • JTAG Debug Interface and Boundary Scan • 5 V Tolerant Digital Inputs (excludes oscillator pins) – XTALIN and XTAL32IN pins are 1.8 V ± 10% • On-Chip regulator allows single 3.3 V supply DESCRIPTION The LH79524/LH79525, powered by an ARM720T, is a complete System-on-Chip with a high level of inte- gration to satisfy a wide range of requirements and applications. The SoC has a fully static design, power management unit, and low voltage operation (1.8 V Core, 3.3 V I/O). With the on-chip voltage regulator, a single 3.3 V supply can be used as well. Robust periph- erals and a low-power RISC core provide high perfor- mance at a reasonable price. 1 1 page System-on-Chip NXP Semiconductors LH79524/LH79525 SIGNAL DESCRIPTIONS Table 2. LH79524 Pin Descriptions LFBGA PIN SIGNAL NAME T12 A0 R11 A1 T11 A2 P10 A3 R10 A4 T10 A5 P9 A6 R9 A7 T9 A8 T8 A9 R8 A10 P8 A11 T7 A12 R7 A13 P7 A14 T6 A15 M15 D0 N16 D1 L13 D2 M14 D3 N15 D4 P16 D5 M13 D6 N14 D7 F14 SDCLK G15 SDCKE D13 DQM0 E13 DQM1 E14 DQM2 G14 DQM3 G16 nDCS0 H14 nDCS1 H15 nRAS H16 nCAS L16 nCS0/PM0 L15 nCS1/PM1 M16 nCS2/PM2 L14 nCS3/PM3 J15 nBLE0/PM4 J14 nBLE1/PM5 K16 nBLE2/PM6 K15 nBLE3/PM7 TYPE DESCRIPTION O External Address Bus I/O External Data Bus O SDRAM Clock O SDRAM Clock Enable O Data Mask Output to SDRAMs O SDRAM Chip Select O SDRAM Chip Select O Row Address Strobe O Column Address Strobe O Static Memory Chip Select; multiplexed with GPIO Port M[3:0] (output only) O Static Memory Byte Lane Enable / Byte Write Enable; multiplexed with GPIO Port M[7:4] (output only) Preliminary data sheet Rev. 01 — 16 July 2007 5 5 Page System-on-Chip NXP Semiconductors LH79524/LH79525 Table 3. LH79524 Numerical Pin List (Cont’d) LFBGA FUNCTION NO. AT RESET MULTIPLEXED FUNCTION(S) G13 VDD G14 DQM3 G15 SDCKE G16 nDCS0 H1 nRESETOUT H2 AN3/LR/Y- PJ0 H3 AN4/WIPER PJ1 H4 VDD H7 VSS H8 VSS H9 VSS H10 VSS H13 VDDC H14 nDCS1 H15 nRAS H16 nCAS J1 VSSA0 J2 nRESETIN J3 CTCLK INT4/BATCNTL J4 VDD J7 VSS J8 VSS J9 VSS J10 VSS J13 VSSC J14 nBLE1 PM5 J15 nBLE0 PM4 J16 nWE K1 CLKOUT K2 PA7 CTCAP2B/ CTCMP2B/SCL K3 PA6 CTCAP2A/ CTCMP2A/SDA K4 VDD K8 VSS K9 VSS K13 VDD K14 nOE K15 nBLE3 PM7 K16 nBLE2 PM6 L1 PA5 CTCAP1B/ CTCMP1B L2 PA4 CTCAP1A/ CTCMP1A L3 PA2 CTCAP0A/ CTCMP0A OUTPUT DRIVE NOTES 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 2, 6 2, 6 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 2, 6 2, 6 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 1, 6 1, 6 1, 6 Table 3. LH79524 Numerical Pin List (Cont’d) LFBGA FUNCTION NO. AT RESET MULTIPLEXED FUNCTION(S) L4 VDD L13 D2 L14 nCS3 PM3 L15 nCS1 PM1 L16 nCS0 PM0 M1 PA3 CTCAP0B/ CTCMP0B M2 PA1 INT3/UARTTX2/ UARTIRTX2 M3 PB7 INT1/UARTTX0/ UARTIRTX0 SSPRX/I2SRXD/ M4 PB4 UARTRX1/ UARTIRRX1 M5 VSS M12 PK1 D17 M13 D6 M14 D3 M15 D0 M16 nCS2 PM2 N1 PA0 INT2/UARTRX2/ UARTIRRX2 N2 PB6 INT0/UARTRX0/ UARTIRRX0 N3 PB3 SSPCLK/I2SCLK N4 VSSC N5 VDDC N6 VDD N7 PC0 A16 N8 VDD N9 VDD N10 VDD N11 PK7 D23 N12 PD4 D12 N13 PD2 D10 N14 D7 N15 D4 N16 D1 SSPTX/I2STXD/ P1 PB5 UARTTX1/ UARTIRTX1 P2 PB2 SSPFRM/I2SWS P3 TDO P4 TMS P5 PC6 A22/nFWE P6 PC3 A19 P7 A14 OUTPUT DRIVE NOTES 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 1 1, 6 1, 6 1, 6 8 mA 2 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 1 1 1 1 1, 6 1, 6 1 8 mA 1 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 4 mA 8 mA 8 mA 8 mA 1 1 1 1 1 1 1 2 2, 6 1 1 Preliminary data sheet Rev. 01 — 16 July 2007 11 11 Page

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