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PDF DM74ALS5245-1 Data sheet ( Hoja de datos )
| Número de pieza | DM74ALS5245-1 | |
| Descripción | Octal 3-STATE Transceiver | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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March 1998
DM74ALS5245/74ALS5245-1
Octal 3-STATE Transceiver
General Description
This octal bus transceiver is designed for asynchronous
two-way communication between data buses. The inputs in-
clude hysteresis which provides improved noise rejection.
Data is transmitted either from the A bus to the B bus or from
the B bus to the A bus depending on the logic level of the di-
rection control (DIR) input. The device can be disabled via
the enable input (G ) which causes the outputs to enter the
high impedance mode so the buses are effectively isolated.
The ALS5245-1 features the same performance as the
ALS5245 with the addition of increased current drive capa-
bility to meet the requirements of various bus architectures.
The recommended maximum IOL is increased to 48 mA.
Features
n Input Hysteresis
n Low output noise generation
n High input noise immunity
n Advanced oxide-isolated, ion implanted Schottky TTL
process
n Switching specification guaranteed over the full
temperature and VCC range
n PNP inputs to reduce input loading
n Maximum IOL is increased to 48 mA for ALS5245-1
Ordering Code:
Order Number Package Number
DM74ALS5245WM
M20B
DM74ALS5245SJ
M20D
DM74ALS5245N
N20A
DM74ALS5245-1WM
M20B
DM74ALS5245-1SJ
M20D
DM74ALS5245-1N
N20A
Package Description
20-Lead Small Outline Package – JEDEC (M)
20-Lead Small Outline Package – EIAJ (SJ)
20-Lead Molded Dual-in-Line Package (N)
20-Lead Small Outline Package – JEDEC (M)
20-Lead Small Outline Package – EIAJ (SJ)
20-Lead Molded Dual-in-Line Package (N)
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
DS009175-1
© 1998 Fairchild Semiconductor Corporation DS009175
www.fairchildsemi.com
1 page  
Switching Characteristics
over recommended operating free air temperature range (Note 7)
Symbol
Parameter
Conditions
tPLH Propagation Delay Time
Low to High Level Output
tPHL Propagation Delay Time
High to Low Level Output
tPZH Output Enable Time
to High Level Output
tPZL Output Enable Time
to Low Level Output
tPHZ Output Disable Time
from High Level Output
tPLZ Output DisableTime
from Low Level Output
VCC = 4.5V to 5.5V,
R1 = R2 = 500Ω,
CL = 50 pF
Note 7: See Section 5 for test waveforms and output load.
From (Input)
To (Output)
A or B to
B or A
A or B to
B or A
G to
A or B
G to
A or B
G to
A or B
G to
A or B
74ALS5245-1
Min Max
2 10
3 10
4 20
5 20
1 10
3 15
Units
ns
ns
ns
ns
ns
ns
5 www.fairchildsemi.com
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet DM74ALS5245-1.PDF ] | |
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