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PDF TH58TEG7DCJTAK0 Data sheet ( Hoja de datos )

Número de pieza TH58TEG7DCJTAK0
Descripción NAND memory Toggle DDR1.0
Fabricantes Toshiba 
Logotipo Toshiba Logotipo



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TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0
TOSHIBA
NAND memory
Toggle DDR1.0
Technical Data Sheet
Rev. 0.3
2012 – 04 – 10
TOSHIBA
Semiconductor & Storage Products
Memory Division
TC58TEG6DCJTA00 / TC58TEG6DCJTAI0
TH58TEG7DCJTA20 / TH58TEG7DCJTAK0
TH58TEG8DCJTA20 / TH58TEG8DCJTAK0
0
TENTATIVE 2012-04-10C

1 page




TH58TEG7DCJTAK0 pdf
TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0
Access time
Cell array to register 100 µs max (TENTATIVE)
50 µs typ.
Data Transfer rate 100MHz
Program/Erase time
Auto Page Program
Auto Block Erase
1700 µs/page typ.
5 ms/block typ.
Operating current
Read
TBD mA max. (per 1 chip)
Program (avg.)
Erase (avg.)
Standby
TBD mA max. (per 1 chip)
TBD mA max. (per 1 chip)
TBD µA max. (per 1 chip)
Package
(Weight: TBD g typ.)
Reliability
Refer to APPLICATION NOTES AND COMMENTS.
1.4. Diagram Legend
Diagrams in the Toggle DDR1.0 datasheet use the following legend:
Command
This legend shows the command data. Refer to the Table 32 for more information about the command data.
Address
C1 C2 R1 R2 R3
This legend shows the Address data. The addresses are comprised of 2 cycles column address and 3 cycles row
address.
C1: Column address 1
C2: Column address 2
R1: Row address 1
R2: Row address 2
R3: Row address 3
W-Data
This legend shows Host writing data (data input) to the device.
R-Data
This legend shows Host reading data (data output) from the device.
SR[x]
This legend shows Host reading the status register within a particular LUN.
TC58TEG6DCJTA00 / TC58TEG6DCJTAI0
TH58TEG7DCJTA20 / TH58TEG7DCJTAK0
TH58TEG8DCJTA20 / TH58TEG8DCJTAK0
4
TENTATIVE 2012-04-10C

5 Page





TH58TEG7DCJTAK0 arduino
TOSHIBA CONFIDENTIAL Tx58TEGxDCJTAx0
2.4. Independent Data Buses
There may be two independent 8-bit data buses in some packages, with two, four or eight CE signals. If the device
supports two independent data buses, then CE 1, CE 3, CE 5, and CE 7 (if connected) shall use the second data
bus. CE 0, CE 2 CE 4, and CE 6 shall always use the first data bus pins. Note that all CE s may use the first
data bus and the first set of control signals ( RE 0, CLE0, ALE0, WE 0, and WP 0) if the device does not support
independent data buses. Table 4 defines the control signal to CE signal mapping when there are two independent
x8 data buses.
Table 4 Dual Channel(x8) Data Bus Signal to CE mapping
Signal Name
R/ B 0
R/ B 1
R/ B 2
R/ B 3
RE 0
RE 1
CLE0
CLE1
ALE0
ALE1
WE 0
WE 1
WP 0
WP 1
DQS0
DQS1
CE
CE 0, CE 4
CE 1, CE 5
CE 2, CE 6
CE 3, CE 7
CE 0, CE 2, CE 4, CE 6
CE 1, CE 3, CE 5, CE 7
CE 0, CE 2, CE 4, CE 6
CE 1, CE 3, CE 5, CE 7
CE 0, CE 2, CE 4, CE 6
CE 1, CE 3, CE 5, CE 7
CE 0, CE 2, CE 4, CE 6
CE 1, CE 3, CE 5, CE 7
CE 0, CE 2, CE 4, CE 6
CE 1, CE 3, CE 5, CE 7
CE 0, CE 2, CE 4, CE 6
CE 1, CE 3, CE 5, CE 7
Implementations may tie the data lines and control signals ( RE , CLE, ALE, WE , WP , and DQS) together for the
two independent 8-bit data buses externally to the device.
2.5. Absolute Maximum DC Rating
Stresses greater than those listing in Table 5 may cause permanent damage to the device. This is a stress rating
only. Operation beyond the operating conditions specified in Table 6 is not recommended. Extended exposure beyond
these conditions may affect device reliability.
Table 5 Absolute Maximum Rating
Parameter
Voltage on any pin relative to VSS
VIN
VI/O
Symbol
VCC
VccQ(3.3V)
VccQ(1.8V)
VccQ(3.3V)
VccQ(1.8V)
Rating
-0.6 to +4.6
-0.6 to +4.6
-0.2 to +2.4
-0.6 to +4.6
-0.2 to +2.4
Unit
V
TC58TEG6DCJTA00 / TC58TEG6DCJTAI0
TH58TEG7DCJTA20 / TH58TEG7DCJTAK0
TH58TEG8DCJTA20 / TH58TEG8DCJTAK0
10
TENTATIVE 2012-04-10C

11 Page







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