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PDF ICE2PCS05G Data sheet ( Hoja de datos )
| Número de pieza | ICE2PCS05G | |
| Descripción | Standalone Power Factor Correction (PFC) Controller | |
| Fabricantes | Infineon Technologies | |
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Version 1.2, 22 Mar 2010
CCM-PFC
ICE2PCS05
ICE2PCS05G
Standalone Power Factor
Correction (PFC) Controller in
Continuous Conduction Mode
(CCM)
Power Management & Supply
Never stop thinking.
1 page  
CCM-PFC
ICE2PCS05/G
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration
Pin Symbol Function
1 GND IC Ground
ICOMP (Current Loop Compensation)
Low pass filter and compensation of the current control
loop. The capacitor which is connected at this pin
integrates the output current of OTA2 and averages the
current sense signal.
2 ICOMP Current Loop Compensation
3 ISENSE Current Sense Input
4 FREQ Switching Frequency Setting
5 VCOMP Voltage Loop Compensation
6 VSENSE VOUT Sense (Feedback) Input
7 VCC IC Supply Voltage
8 GATE Gate Drive Output
ISENSE (Current Sense Input)
The ISENSE Pin senses the voltage drop at the
external sense resistor (R1). This is the input signal for
the average current regulation in the current loop. It is
also fed to the peak current limitation block.
During power up time, high inrush currents cause high
negative voltage drop at R1, driving currents out of pin
3 which could be beyond the absolute maximum
ratings. Therefore a series resistor (R2) of around
220W is recommended in order to limit this current into
the IC.
Package PG-DIP-8 / PG-DSO-8
FREQ (Frequency Setting)
This pin allows the setting of the operating switching
frequency by connecting a resistor to ground. The
frequency range is from 20kHz to 250kHz.
GND
1
ICOMP
2
ISENSE
3
FREQ
4
8 GATE
7 VCC
6 VSENSE
5 VCOMP
VSENSE (Voltage Sense/Feedback)
The output bus voltage is sensed at this pin via a
resistive divider. The reference voltage for this pin is
3V.
VCOMP (Voltage Loop Compensation)
This pin provides the compensation of the output
voltage loop with a compensation network to ground
(see Figure 2). This also gives the soft start function
which controls an increasing AC input current during
start-up.
Figure 1 Pin Configuration (top view)
VCC (Power Supply)
The VCC pin is the positive supply of the IC and should
be connected to an external auxiliary supply. The
operating range is between 11V and 26V. The turn-on
threshold is at 11.8V and under voltage occurs at 11V.
There is no internal clamp for a limitation of the power
supply.
1.2 Pin Functionality
GND (Ground)
The ground potential of the IC.
GATE
The GATE pin is the output of the internal driver stage,
which has a capability of 1.5A instantaneous source
and 2.0A instantaneous sink current.
Its gate drive voltage is clamped at 15V (typically).
Version 1.2
5 22 Mar 2010
5 Page 
voltage at pin VCOMP. This block has been designed
to support the wide input voltage range (85-265VAC).
3.7 PWM Logic
The PWM logic block prioritizes the control input
signals and generates the final logic signal to turn on
the driver stage. The speed of the logic gates in this
block, together with the width of the reset pulse TOFFMIN,
are designed to meet a maximum duty cycle DMAX of
95% at the GATE output under 136kHz of operation.
In case of high input currents which result in Peak
Current Limitation, the GATE will be turned off
immediately and maintained in off state for the current
PWM cycle. The signal Toffmin resets (highest priority,
overriding other input signals) both the current limit
latch and the PWM on latch as illustrated in Figure 14.
CCM-PFC
ICE2PCS05/G
Functional Description
From
Full-wave
Retifier
L1
R7
D1 R3 Vout
C2
R4
Current Loop
+
PWM Generation
VIN
Av(IIN)
Nonlinear
Gain
t
Gate Driver
GATE
OTA1
3V
VSENSE
Peak Current
Limit
Current Loop
PWM on signal
Toffmin
2.5% of T
Current
Limit Latch
Q
S
L1
R
PWM on
Latch
S
L2 Q
R
G1 HIGH =
turn GATE on
Figure 14 PWM Logic
3.8 Voltage Loop
The voltage loop is the outer loop of the cascaded
control scheme which controls the PFC output bus
voltage VOUT. This loop is closed by the feedback
sensing voltage at VSENSE which is a resistive divider
tapping from VOUT. The pin VSENSE is the input of
OTA1 which has an internal reference of 3V. Figure 15
shows the important blocks of this voltage loop.
VCOMP
R6
C4 C5
Figure 15 Voltage Loop
3.8.2 Enhanced Dynamic Response
Due to the low frequency bandwidth of the voltage loop,
the dynamic response is slow and in the range of about
several 10ms. This may cause additional stress to the
bus capacitor and the switching transistor of the PFC in
the event of heavy load changes.
The IC provides therefore a “window detector” for the
feedback voltage VVSENSE at pin 6 (VSENSE).
Whenever VVSENSE exceeds the reference value (3V)
by +5%, it will act on the nonlinear gain block which in
turn affect the gate drive duty cycle directly. This
change in duty cycle is bypassing the slow changing
VCOMP voltage, thus results in a fast dynamic
response of VOUT.
3.8.1 Voltage Loop Compensation
The compensation of the voltage loop is installed at the
VCOMP pin (see Figure 15). This is the output of OTA1
and the compensation must be connected at this pin to
ground. The compensation is also responsible for the
soft start function which controls an increasing AC input
current during start-up.
3.9 Output Gate Driver
The output gate driver is a fast totem pole gate drive. It
has an in-built cross conduction currents protection and
a Zener diode Z1 (see Figure 16) to protect the external
transistor switch against undesirable over voltages.
The maximum voltage at pin 8 (GATE) is typically
clamped at 15V.
The output is active HIGH and at VCC voltages below
the under voltage lockout threshold VCCUVLO, the gate
drive is internally pull low to maintain the off state.
Version 1.2
11 22 Mar 2010
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