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PDF 80C286-883 Data sheet ( Hoja de datos )

Número de pieza 80C286-883
Descripción 80C286/883 High Performance Microprocessor
Fabricantes Intersil 
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No Preview Available ! 80C286-883 Hoja de datos, Descripción, Manual

80C286/883
March 1997
High Performance Microprocessor with Memory
Management and Protection
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Compatible with NMOS 80286/883
• Static CMOS Design for Low Power Operation
- ICCSB = 5mA Maximum
- ICCOP = 185mA Maximum (80C286-10/883)
- ICCOP = 220mA Maximum (80C286-12/883)
• Large Address Space
- 16 Megabytes Physical
- 1 Gigabyte Virtual per Task
• Integrated Memory Management, Four-Level Memory
Protection and Support for Virtual Memory and
Operating Systems
• Two 80C86 Upward Compatible Operating Modes
- 80C286/883 Real Address Mode
- Protected Virtual Address Mode
• Compatible with 80287 Numeric Data Co-Processor
The Intersil 80C286/883 is a static CMOS version of the
NMOS 80286 microprocessor. The 80C286/883 is an
advanced, high-performance microprocessor with specially
optimized capabilities for multiple user and multi-tasking sys-
tems. The 80C286/883 has built-in memory protection that
supports operating system and task isolation as well as pro-
gram and data privacy within tasks. The 80C286/883
includes memory management capabilities that map 230
(one gigabyte) of virtual address space per task into 224
bytes (16 megabytes) of physical memory.
The 80C286/883 is upwardly compatible with 80C86 and
80C88 software (the 80C286/883 instruction set is a super-
set of the 80C86/80C88 instruction set). Using the 80C286/
883 real address mode, the 80C286/883 is object code com-
patible with existing 80C86 and 80C88 software. In protected
virtual address mode, the 80C286/883 is source code com-
patible with 80C86 and 80C88 software but may require
upgrading to use virtual address as supported by the
80C286/883’s integrated memory management and protec-
tion mechanism. Both modes operate at full 80C286/883
performance and execute a superset of the 80C86 and
80C88 instructions.
The 80C286/883 provides special operations to support the
efficient implementation and execution of operating systems.
For example, one instruction can end execution of one task,
save its state, switch to a new task, load its state, and start
execution of the new task. The segment-not-present excep-
tion and restartable instructions.
Ordering Information
PACKAGE TEMP. RANGE
10MHz
12.5MHz
16MHz
68 Pin PGA 0oC to +70oC
-
CG80C286-12
CG80C286-16
-40oC to +85oC IG80C286-10
IG80C286-12
-
-55oC to +125oC MG80C286-10/883 MG80C286-12/883
-
5962-9067801MXC 5962-9067802MXC
-
20MHz
CG80C286-20
-
-
-
25MHz
-
-
-
-
PKG. NO.
G68.B
G68.B
G68.B
G68.B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-128
File Number 2948.1

1 page




80C286-883 pdf
80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
80C286/883
PARAMETER
HLDA Valid Delay
(Note 5)
SYMBOL CONDITIONS
15 VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
GROUP A
SUBGROUPS TEMPERATURE
10MHz
12.5MHz
MIN MAX MIN MAX UNITS
9, 10, 11
-55oC TA +125oC 0
47
0
25
ns
NOTES:
1. Asynchronous inputs are INTR, NMI, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure
recognition at a specific CLK edge.
2. Delay from 1.0V on the CLK to 0.8V or 2.0V.
3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay).
4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay).
5. Delay from 1.0V on the CLK to 2.0V.
TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
80C286/883
10MHz
12.5MHz
PARAMETER
SYMBOL CONDITIONS NOTES
TEMPERATURE MIN MAX MIN MAX UNITS
CLK Input Capacitance
CCLK
FREQ = 1MHz
5
TA = +25oC
- 10 - 10 pF
Other Input Capacitance
CIN FREQ = 1MH
5
TA = +25oC
- 10 - 10 pF
I/O Capacitance
CI/O FREQ = 1MH
5
TA = +25oC
- 10 - 10 pF
Address/Status/Data
Float Delay
15
1, 3, 4, 5 -55oC TA +125oC
0
47
0
32
ns
Address Valid to Status
SETUP Time
19 IL = | 2.0mA| 1, 2, 5 -55oC TA +125oC 27 - 20 -
ns
NOTES:
1. Output Load: CL = 100pF.
2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching
2.0V.
3. Delay from 1.0V on the CLK to Float (no current drive) condition.
4. IL = -6mA (VOH to Float), IL = 8mA (VOL to Float).
5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-
acterized upon initial design and after major process and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Group C & D
METHOD
100%/5004
100%/5004
100%
100%
-
Samples/5005
SUBGROUPS
-
1, 7, 9
1
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
3-132

5 Page





80C286-883 arduino
80C286/883
Waveforms (Continued)
BUS CYCLE TYPE
CLK
HOLD
BUS HOLD ACKNOWLEDGE
TH
φ1 φ2
TH
φ1 φ2
TH
φ1 φ2
TS
φ1 φ2
WRITE CYCLE
TC
φ1 φ2
TC
φ1 φ2
TC
φ1 φ2
BUS HOLD
ACKNOWLEDGE
TI
φ1 φ2
TH
φ1 φ2
(SEE NOTE 4)
(SEE NOTE 5)
(SEE NOTE 6)
HLDA
(SEE NOTE 1)
S1 S0
A23 - A0
M/IO,
COD/INTA
BHE, LOCK
VALID
VALID
(SEE NOTE 2)
(SEE NOTE 3)
(SEE NOTE 1)
D15 - D0
SRDY +
SRDYEN
ARDY +
ARDYEN
CMDLY
MWTC
VOH
DT/R
DEN
VALID
NOT READY NOT READY (SEE NOTE 7)
NOT READY NOT READY
READY
DELAY ENABLE
(SEE NOTE 7)
ALE
TS - STATUS CYCLE
CT - COMMAND CYCLE
NOTES:
1. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.
2. Address, M/IO and COD/lNTA may start floating during any TC depending on when internal 80C286 bus arbiter decides to release bus to
external HOLD. The float starts in φ2 of TC.
3. BHE and LOCK may start floating after the end of any TC depending on when internal 80C286 bus arbiter decides to release bus to ex-
ternal HOLD. The float starts in φ1 of TC.
4. The minimum HOLD to HLDA time is shown. Maximum is one TH longer.
5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
6. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,
Interrupts, Waits, Lock, etc.).
7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state
is ignored after ready is signaled via the asynchronous input.
FIGURE 8. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD
3-138

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