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PDF MAX13001E Data sheet ( Hoja de datos )
| Número de pieza | MAX13001E | |
| Descripción | Ultra-Low-Voltage Level Translators | |
| Fabricantes | Maxim Integrated | |
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19-3692; Rev 1; 5/11
Ultra-Low-Voltage Level Translators
General Description
The MAX13000E–MAX13005E 6-channel level transla-
tors provide the level shifting necessary to allow data
transfer in multivoltage systems. Externally applied volt-
ages, VCC and VL, set the logic levels on either side of
the device. Logic signals present on the VL side of the
device appear as higher voltage logic signals on the
VCC side of the device, and vice-versa.
The MAX13000E–MAX13005E feature a low VCC and VL
quiescent supply current less than 4µA. The
MAX13000E–MAX13005E also have ±15kV ESD protec-
tion on the I/O VCC side for greater protection in applica-
tions that route signals externally. The ESD protection is
specified using the Human Body Model (HBM). The
MAX13000E/MAX13001E/MAX13002E operate at a guar-
anteed 230kbps data rate. The MAX13003E/
MAX13004E/MAX13005E operate at a guaranteed
20Mbps data rate when VCC > +1.65V.
The MAX13000E/MAX13003E are bidirectional level
translators, allowing data translation in either direction
(VL ↔ VCC) on any single data line without a DIRECTION
input. The MAX13001E/MAX13002E/MAX13004E/
MAX13005E unidirectional level translators level shift
data in one direction (VL → VCC or VCC → VL) on any
single data line. The MAX13001E/MAX13002E/
MAX13004E/MAX13005E unidirectional translators’
inputs have the capability to interface with both CMOS
and open-drain (OD) outputs. For more information see
the Ordering Information, Selector Guide, and the Input-
Driver Requirements sections.
The MAX13000E–MAX13005E operate with +0.9V to
+3.6V VL voltages and +1.5V to +3.6V VCC voltages. The
MAX13000E–MAX13005E are available in 16-bump
UCSP™ and 16-pin TSSOP packages, and are specified
over the extended -40°C to +85°C operating tempera-
ture range.
Applications
CMOS Logic-Level Translation
Open-Drain I/O Translation
OD-to-CMOS Signal Conversion
Low-Voltage ASIC Level Translation
Cell Phones
SPI™ and MICROWIRE® Level Translation
Smart-Card Readers
Portable POS Systems
Portable Communication Devices
Low-Cost Serial Interfaces
Telecommunications Equipment
Features
♦ Guaranteed Data-Rate Options
230kbps (MAX13000E/MAX13001E/MAX13002E)
20Mbps (MAX13003E/MAX13004E/MAX13005E)
♦ Bidirectional Level Translation Without a
DIRECTION Input
♦ Operational Down to +0.9V on VL and +1.5V on VCC
♦ ±15kV ESD Protection on I/O VCC Lines per HBM
♦ Low <4µA Quiescent Current
♦ Enable/Shutdown Control
♦ 2mm x 2mm, 16-Bump UCSP and Lead Packaging
Options
♦ CMOS or Open-Drain Outputs Interface Capability
UCSP is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
Ordering Information
PART
TEMP RANGE
PIN-
PACKAGE
MAX13000EEUE+
-40°C to +85°C
16 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Ordering Information continued at end of data sheet.
Pin Configurations
BOTTOM VIEW
MAX13000E/MAX13003E
I/OVCC3 VCC
GND I/OVCC4
D
I/OVCC1 I/OVCC2 I/OVCC5 I/OVCC6
C
I/OVL1 I/OVL2 I/OVL5 I/OVL6
B
I/OVL3
VL
EN I/OVL4
A
1 234
4 X 4 UCSP
Pin Configurations continued at end of data sheet.
Typical Operating Circuits and Selector Guide appear at end
of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
Ultra-Low-Voltage Level Translators
TIMING CHARACTERISTICS (continued)
(VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA = +25°C.) (Notes 1, 4)
PARAMETER
SYMBOL
CONDITIONS
CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 2a, 2b
MIN TYP MAX UNITS
15
I/OVL_ Rise Time
CI/OVL = 15pF,
tRVL MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 2a, 2b
15 ns
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
300
1200
CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 2a, 2b
15
I/OVL_ Fall Time
CI/OVL = 15pF,
tFVL MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 2a, 2b
15 ns
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
300
1200
Propagation Delay
(Driving I/OVL_)
I/OVL-VCC
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 1a, 1b
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
20
1000
ns
VCC > +1.65V, CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 2a, 2b
20
Propagation Delay
(Driving I/OVCC_)
VCC = 1.5V, CI/OVL = 15pF,
I/OVCC-VL MAX13003E/MAX13004E/MAX13005E,
Figures 2a, 2b
20 ns
Propagation Delay from
I/OVL to I/OVCC_ after EN
(Note 5)
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
tEN-VCC
CI/OVCC = 50pF, CMOS output, Figure 3
CI/OVCC = 50pF, OD output, Figure 3
1000
2
6
µs
_______________________________________________________________________________________ 5
5 Page 
Ultra-Low-Voltage Level Translators
MAX13002E/MAX13005E
PIN
TSSOP
1
2
3
UCSP
B1
B2
A1
4 A2
NAME
IVL1
IVL2
IVL3
VL
5 A3
EN
6 A4 IVL4
7 B3 IVL5
8 B4 IVL6
9 C4 OVCC6
10 C3 OVCC5
11 D4 OVCC4
12 D3
GND
13 D2
VCC
14 D1 OVCC3
15 C2 OVCC2
16 C1 OVCC1
Pin Descriptions (continued)
FUNCTION
Open-Drain-Compatible Input 1, Referenced to VL
Open-Drain-Compatible Input 2, Referenced to VL
Open-Drain-Compatible Input 3, Referenced to VL
Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF
capacitor.
Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are
tri-stated. Drive EN high (VL) for normal operation.
Open-Drain-Compatible Input 4, Referenced to VL
Open-Drain-Compatible Input 5, Referenced to VL
Open-Drain-Compatible Input 6, Referenced to VL
CMOS Output 6, Referenced to VCC
CMOS Output 5, Referenced to VCC
CMOS Output 4, Referenced to VCC
Ground
VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF
capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC.
CMOS Output 3, Referenced to VCC
CMOS Output 2, Referenced to VCC
CMOS Output 1, Referenced to VCC
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet MAX13001E.PDF ] | |
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