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PDF LAN9352 Data sheet ( Hoja de datos )
| Número de pieza | LAN9352 | |
| Descripción | 2-Port 10/100 Managed Ethernet Switch | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LAN9352 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LAN9352
2-Port 10/100 Managed Ethernet Switch with
8/16-Bit Non-PCI CPU Interface
Highlights
• High performance 2-port switch with VLAN, QoS
packet prioritization, rate limiting, IGMP monitoring
and management functions
• Interfaces to most 8/16-bit embedded controllers
and 32-bit embedded controllers with an 8/16-bit
bus
• Integrated Ethernet PHYs with HP Auto-MDIX
• Compliant with Energy Efficient Ethernet 802.3az
• Wake on LAN (WoL) support
• Integrated IEEE 1588v2 hardware time stamp unit
• Cable diagnostic support
• 1.8V to 3.3V variable voltage I/O
• Integrated 1.2V regulator for single 3.3V operation
Target Applications
• Cable, satellite, and IP set-top boxes
• Digital televisions & video recorders
• VoIP/Video phone systems, home gateways
• Test/Measurement equipment, industrial automation
Key Benefits
• Ethernet Switch Fabric
- 32K buffer RAM, 512 entry forwarding table
- Port based IEEE 802.1Q VLAN support (16 groups)
- Programmable IEEE 802.1Q tag insertion/removal
- IEEE 802.1D spanning tree protocol support
- 4 separate transmit queues available per port
- Fixed or weighted egress priority servicing
- QoS/CoS Packet prioritization
- Input priority determined by VLAN tag, DA lookup, TOS,
DIFFSERV or port default value
- Programmable Traffic Class map based on input priority
on per port basis
- Remapping of 802.1Q priority field on per port basis
- Programmable rate limiting at the ingress with coloring
and random early discard, per port / priority
- Programmable rate limiting at the egress with leaky
bucket algorithm, per port / priority
- IGMP v1/v2/v3 monitoring for Multicast packet filtering
- Programmable broadcast storm protection with global %
control and enable per port
- Programmable buffer usage limits
- Dynamic queues on internal memory
- Programmable filter by MAC address
• Switch Management
- Port mirroring/monitoring/sniffing: ingress and/or egress
traffic on any port or port pair
- Fully compliant statistics (MIB) gathering counters
• Ports
- 2 internal 10/100 PHYs with HP Auto-MDIX
support
- Fully compliant with IEEE 802.3 standards
- 10BASE-T and 100BASE-TX support
- 100BASE-FX support via external fiber transceiver
- Full and half duplex support, full duplex flow control
- Backpressure (forced collision) half duplex flow control
- Automatic flow control based on programmable levels
- Automatic 32-bit CRC generation and checking
- Programmable interframe gap, flow control pause value
- Auto-negotiation, polarity correction & MDI/MDI-X
• 8/16-Bit Host Bus Interface
- Indexed register or multiplexed bus
- SPI / Quad SPI support
• IEEE 1588v2 hardware time stamp unit
- Global 64-bit tunable clock
- Boundary clock: master / slave, one-step / two-step,
end-to-end / peer-to-peer delay
- Transparent Clock with Ordinary Clock:
master / slave, one-step / two-step, end-to-end / peer-
to-peer delay
- Fully programmable timestamp on TX or RX,
timestamp on GPIO
- 64-bit timer comparator event generation (GPIO or IRQ)
• Comprehensive power management features
- 3 power-down levels
- Wake on link status change (energy detect)
- Magic packet wakeup, Wake on LAN (WoL), wake on
broadcast, wake on perfect DA
- Wakeup indicator event signal
• Power and I/O
- Integrated power-on reset circuit
- Latch-up performance exceeds 150mA
per EIA/JESD78, Class II
- JEDEC Class 3A ESD performance
- Single 3.3V power supply
(integrated 1.2V regulator)
• Additional Features
- Multifunction GPIOs
- Ability to use low cost 25MHz crystal for reduced BOM
• Packaging
- Pb-free RoHS compliant 72-pin QFN or 80-pin TQFP-
EP
• Available in commercial and industrial temp. ranges
2015 Microchip Technology Inc.
DS00001923A-page 1
1 page  
LAN9352
TABLE 1-1: GENERAL TERMS (CONTINUED)
Term
Description
NRZI
N/A
NC
OUI
Outbound
PISO
PLL
PTP
RESERVED
RTC
SA
SFD
SIPO
SMI
SQE
SSD
UDP
UUID
WORD
Non Return to Zero Inverted. This encoding method inverts the signal for a “1” and
leaves the signal unchanged for a “0”
Not Applicable
No Connect
Organizationally Unique Identifier
Refers to data output from the device to the host
Parallel In Serial Out
Phase Locked Loop
Precision Time Protocol
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
Real-Time Clock
Source Address
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an
Ethernet frame.
Serial In Parallel Out
Serial Management Interface
Signal Quality Error (also known as “heartbeat”)
Start of Stream Delimiter
User Datagram Protocol - A connectionless protocol run on top of IP networks
Universally Unique IDentifier
16 bits
2015 Microchip Technology Inc.
DS00001923A-page 5
5 Page 
LAN9352
Table 3-1 details the 72-QFN package pin assignments in table format. As shown, select pin functions may change
based on the device’s mode of operation. For modes where a specific pin has no function, the table cell will be marked
with “-”.
TABLE 3-1:
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
72-QFN PACKAGE PIN ASSIGNMENTS
HBI Indexed Mode
Pin Name
D2
D1
D14
D13
D0
D9
D12
D11
D10
A1
A3
A4
HBI Multiplexed Mode
Pin Name
OSCI
OSCO
OSCVDD12
OSCVSS
VDD33
VDDCR
REG_EN
FXLOSEN
FXSDA/FXLOSA/FXSDENA
FXSDB/FXLOSB/FXSDENB
RST#
GPIO7
GPIO6
AD2
AD1
VDDIO
AD14
AD13
AD0
PME
LED5/GPIO5/PHYADD
LED4/GPIO4/1588EN
AD9
VDDIO
AD12
AD11
AD10
VDDCR
ALELO
MNGT2
MNGT3
CS
SPI Mode
Pin Name
SIO2
SO/SIO1
-
-
SI/SIO0
SCK
-
-
-
-
-
-
-
2015 Microchip Technology Inc.
DS00001923A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LAN9352.PDF ] | |
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