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PDF CL12464FF Data sheet ( Hoja de datos )
| Número de pieza | CL12464FF | |
| Descripción | LVDS Receiver 24bit FPD-link 85MHz | |
| Fabricantes | CURIOUS | |
| Logotipo |  |
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CL12464FF
LVDS Receiver 24bit FPD-link 85MHz
Introduction
The CL12464FF receiver converts serial four LVDS data streams data back into parallel 28bits (24bits of
RGB data and 4bits of HSYNC, VSYNC, DE and Control1) of LVCMOS parallel. The CL12464FF
receiver’ outputs are Falling edge clock. The CL12464FF receiver is an ideal means to solve EMI and cable
size problems associated with wide, high-speed LVCMOS interfaces.
Feature
■ Input Clock: 20MHz~85MHz Input Data Rate: 140Mbps~595Mbps
■ Output Clock: 20MHz to 85MHz shift clock support
■ Low power single 3.3V
■ A falling edge strobe
■ Supports VGA, SVGA, XGA, SXGA, SXGA+
■ Narrow bus reduces cable size
■ PLL requires no external components
■ Power down mode
■ Low Profile 56 Lead TSSOP Package
■ 345mV swing LVDS devices for low EMI
■ Supports Fail-Safe function to all input channels
■ Pin Compatible with DS90C384/386, THC63LVDM84B
Block Diagram
CURIOUS Corporation
1
Rev. 1.00
1 page  
CL12464FF
4. Switching Characteristics
Symbol
Parameter
RCOP RxCLK OUT Period
RCOH RxCLK OUT High Time
RCOL RxCLK OUT Low Time
CLHT LVCMOS Low to High Transition Time
CHLT LVCMOS High to Low Transition Time
RSPOS0
RSPOS1
RSPOS2
RSPOS3
RSPOS4
RSPOS5
RSPOS6
RSRC
Receiver Input Strobe Position for Bit 0
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxOUT Setup to RxCLK OUT
RHRC RxOUT Hold to RxCLK OUT
RCCD RxCLK IN to RxCLK OUT Delay
RPLLS Receiver Phase Lock Loop Set
RPDD Receiver Power Down Delay
LVDS Receiver 24bit FPD-link 85MHz
Vcc=3.0V to 3.6V Ta=-10℃ to 70℃
min typ max unit
7.41 T
50
T/2
T/2 ns
13
13
-0.5 0 +0.5
T/7-0.5 T/7 T/7+0.5
2T/7-0.5 2T/7 2T/7+0.5
3T/7-0.5 3T/7 3T/7+0.5 ns
4T/7-0.5 4T/7 4T/7+0.5
5T/7-0.5 5T/7 5T/7+0.5
6T/7-0.5 6T/7 6T/7+0.5
T/2-2.5
T/2-2.5
ns
4T/7
10 ms
1 us
Fail-Safe Function
The CL12464FF receiver output ”high” when the differential inputs is :
1) Open
2) Undriven and Shorted
3) Undriven and Terminated
CURIOUS Corporation
5
Rev. 1.00
5 Page 
CL12464FF
Modification History
Version
1.00
0.30
Date
2010 / 1 / 12
2007 / 7 / 18
0.20 2006 / 5 / 23
0.10 2005 / 5 / 10
0.00 2003 / 5 / 15
LVDS Receiver 24bit FPD-link 85MHz
Contents
1) Block Diagram changed
1) Input Clock frequency & Data rate added
1) From CL12464AF to CL12464FF changed
2) Fail-Safe Function added
3) Package LOGO changed
4) Supply Current value changed
5) Maximum Dot Clock Frequency cjanged
6) IOL value changed for Changing Frequency
7) The output Rising/Falling Time value changed
8) RxCLK OUT Cycle Time Changed
Fig.2 Modified turn of Pin Name and Signal
First Version
CURIOUS Corporation
11
Rev. 1.00
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CL12464FF.PDF ] | |
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