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PDF PCA9654E Data sheet ( Hoja de datos )
| Número de pieza | PCA9654E | |
| Descripción | 8-bit I/O Expander | |
| Fabricantes | ON Semiconductor | |
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PCA9654E, PCA9654EA
8-bit I/O Expander for I2C
Bus and SMBus with
Interrupt
The PCA9654E/PCA9654EA provides 8 bits of General Purpose
parallel Input/Output (GPIO) expansion for I2C−bus/SMBus
applications.
The PCA9654E/PCA9654EA consists of 8−bit Configuration
(Input or Output selection), Input, Output and Polarity Inversion
(active HIGH or active LOW operation) registers. The system master
may set the I/Os as either inputs or outputs by writing to the I/O
configuration bits. The data for each Input or Output is kept in the
corresponding Input or Output register. The polarity of the read
register can be inverted with the Polarity Inversion register. All
registers can be read by the system master.
The PCA9654E/PCA9654EA open−drain interrupt (INT) output is
activated when any input state differs from its corresponding input
port register state and is used to indicate to the system master that an
input state has changed. The power−on reset sets the registers to their
default values and initializes the device state machine.
Three hardware pins (AD0, AD1, AD2) vary the fixed I2C bus
address and allow up to 64 devices to share the same I2C−bus/SMBus.
The PCA9654EA has a different address map from the PCA9654E.
Features
• VDD Operating Range: 1.65 V to 5.5 V
• SDA Sink Capability: 30 mA
• 5.5 V Tolerant I/Os
• Polarity Inversion Register
• Active LOW Interrupt Output
• Low Standby Current
• Noise Filter on SCL/SDA Inputs
• No Glitch on Power−up
• Internal Power−on Reset
• 64 Programmable Slave Addresses Using 3 Address Pins
• 8 I/O Pins which Default to 8 Inputs
• I2C SCL Clock Frequencies Supported:
Standard Mode: 100 kHz
Fast Mode: 400 kHz
Fast Mode +: 1 MHz
• ESD Performance: 4000 V Human Body Model,
400 V Machine Model
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
www.onsemi.com
1
SOIC−16
D SUFFIX
CASE 751B
MARKING
DIAGRAMS
16
PCA9654EG
AWLYWW
1
1
TSSOP−16
DT SUFFIX
CASE 948F
1
WQFN16
MT SUFFIX
CASE 488AP
1
QFN16 3x3
MN SUFFIX
CASE 485G
16
PCA9
654E
ALYWG
G
1
16
1
XXMG
G
16
1 XXXX
XXXX
ALYWG
G
1
QFN16 4x4
MN SUFFIX
CASE 485AP
16
1 XXXXXX
XXXXXX
ALYWG
G
XXXX = Specific Device Code
A = Assembly Location
M = Date Code / Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
February, 2015 − Rev. 2
1
Publication Order Number:
PCA9654E/D
1 page  
PCA9654E, PCA9654EA
Table 4. DC ELECTRICAL CHARACTERISTICS VDD = 1.65 V to 5.5 V, unless otherwise specified.
TA = −555C to +1255C
Symbol
Parameter
Conditions
Min Typ Max
Unit
SUPPLIES
IDD Supply Current
ISTB Standby Current
VPOR
Power−On Reset Voltage (Note 6)
INPUT SCL; Input / Output SDA
Operating mode; no load;
VI = VDD or 0 V; fSCL = 1 MHz
VI = VDD or 0 V; fSCL = 100 kHz
Standby mode; no load;
VI = 0 V; fSCL = 0 Hz; I/O = inputs
VI = VDD; fSCL = 0 Hz; I/O = inputs
250 500
104 175
550 700
0.25 1
1.5
mA
mA
V
VIH
VIL
IOL
IL
CI
I/Os
High−Level Input Voltage
Low−Level Input Voltage
Low−Level Output Current
Leakage Current
Input Capacitance
VOL = 0.4 V; VDD < 2.3 V
VOL = 0.4 V; VDD w 2.3 V
VI = VDD or GND
VI = GND
0.7 x VDD
10
20
0.3 x VDD
V
V
mA
$1 mA
6 pF
VIH High−Level Input Voltage
VIL Low−Level Input Voltage
IOL Low−Level Output Current
(Note 7)
2.3 V ≤ VCC ≤ 5.5 V
1.65 V ≤ VCC ≤ 2.3 V
2.3 V ≤ VCC ≤ 5.5 V
1.65 V ≤ VCC ≤ 2.3 V
VOL = 0.5 V; VDD = 1.65 V
VOL = 0.5 V; VDD = 2.3 V
VOL = 0.5 V; VDD = 3.0 V
VOL = 0.5 V; VDD = 4.5 V
2.0
0.7 x VDD
V
0.8
0.3 x VDD
V
8 13
12 22
17 28
25 37
mA
IOL(tot)
Total Low−Level Output Current
(Note 7)
VOL = 0.5 V; VDD = 4.5 V
200 mA
VOH High−Level Output Voltage
ILH Input Leakage Current
ILL Input Leakage Current
CI/O Input / Output Capacitance
(Note 8)
IOH = −3 mA; VDD = 1.65 V
IOH = −4 mA; VDD = 1.65 V
IOH = −8 mA; VDD = 2.3 V
IOH = −10 mA; VDD = 2.3 V
IOH = −8 mA; VDD = 3.0 V
IOH = −10 mA; VDD = 3.0 V
IOH = −8 mA; VDD = 4.5 V
IOH = −10 mA; VDD = 4.5 V
VDD = 5.5 V; VI = VDD
VDD = 5.5 V; VI = GND
1.2 V
1.1
1.8
1.7
2.6
2.5
4.1
4.0
1
−100
mA
mA
3.7 5 pF
INTERRUPT (INT)
IOL Low−Level Output Current
CO Output Capacitance
INPUTS AD0, AD1, AD2
VOL = 0.4 V
6 mA
2.1 5 pF
VIH High−Level Input Voltage
2.3 V ≤ VCC ≤ 5.5 V
1.65 V ≤ VCC ≤ 2.3 V
2.0
0.7 x VDD
V
VIL Low−Level Input Voltage
2.3 V ≤ VCC ≤ 5.5 V
1.65 V ≤ VCC ≤ 2.3 V
0.8
0.3 x VDD
V
IL Leakage Current
VI = VDD or GND
$1 mA
CI Input Capacitance
2.4 5 pF
6. The power−on reset circuit resets the I2C bus logic with VDD < VPOR and set all I/Os to logic 1 upon power−up. Thereafter, VDD must be lower
than 0.2 V to reset the part.
7. Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal bussing limits.
8. The value is not tested, but verified on sampling basis.
www.onsemi.com
5
5 Page 
PCA9654E, PCA9654EA
REGISTERS
Command Byte
Table 8. COMMAND BYTE
COMMAND
0
1
2
3
PROTOCOL
Read byte
Read / Write byte
Read / Write byte
Read / Write byte
REGISTER
Input Port
Output Port
Polarity Inversion
Configuration
The command byte is the first byte to follow the address
byte during a write transmission. It is used as a pointer to
determine which of the following registers will be written or
read.
Register 0 − Input Port Register
This register is a read−only port. It reflects the incoming
logic levels of the pins, regardless of whether the pin is
defined as an input or an output by Register 3. Writes to this
register have no effect.
The default ‘X’ is determined by the externally applied
logic level, normally ‘1’ when no external signal externally
applied because of the internal pull−up resistors.
Table 9. INPUT PORT REGISTER
Bit 7 6 5 4 3 2 1 0
Symbol
I7
I6
I5
I4
I3
I2
I1
I0
Access
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
Register 1 − Output Port Register
This register reflects the outgoing logic levels of the pins
defined as outputs by Register 3. Bit values in this register
have no effect on pins defined as inputs. Reads from this
register return the value that is in the flip−flop controlling the
output selection, not the actual pin value.
Table 10. OUTPUT PORT REGISTER
Bit 7 6 5 4 3 2 1 0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Default
1
1
1
1
1
1
1
1
Register 2 − Polarity Inversion Register
This register allows the user to invert the polarity of the
Input Port register data. If a bit in this register is set (written
with ‘1’), the corresponding Input Port data is inverted. If a
bit in this register is cleared (written with a ‘0’), the Input
Port data polarity is retained.
Table 11. POLARITY INVERSION REGISTER
Bit 7 6 5 4 3 2 1 0
Symbol
N7
N6
N5
N4
N3
N2
N1
N0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Default
0
0
0
0
0
0
0
0
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11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet PCA9654E.PDF ] | |
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