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PDF A3V56S30GTP Data sheet ( Hoja de datos )
| Número de pieza | A3V56S30GTP | |
| Descripción | 256M Single Data Rate Synchronous DRAM | |
| Fabricantes | Zentel | |
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A3V56S30GTP
A3V56S40GTP
256M Single Data Rate Synchronous DRAM
256Mb Synchronous DRAM Specification
A3V56S30GTP
A3V56S40GTP
Industrial Version
Zentel Electronics Corp.
I Revision 1.0
Jun., 2013
1 page  
A3V56S30GTP
A3V56S40GTP
256M Single Data Rate Synchronous DRAM
Pin Descriptions
SYMBOL
TYPE
DESCRIPTION
CLK
CKE
/CS
/CAS, /RAS,
/WE
DQM,
LDQM,
UDQM,
BA0, BA1
A0–A12
DQ0–DQ15
NC
VDDQ
VSSQ
VDD
VSS
Input
Input
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK.
CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides
PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN
(row active in any bank), or CLOCK SUSPEND operation (burst / access in progress). CKE is synchronous
except after the device enters self refresh mode, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during self refresh mode, providing low standby
power. CKE may be tied HIGH.
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems
with multiple banks. /CS is considered part of the command code.
Input
Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.
Input
Input
Input
I/O
–
Supply
Supply
Supply
Supply
Input / Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output
disable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed
in a High-Z state (two-clock latency) when during a READ cycle. DQM corresponds to DQ0–DQ7
(A3V56S30GTP). LDQM corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15 (A3V56S40GTP).
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE
command is being applied.
A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12.
The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option.
When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a
precharge command, all banks are precharged.
Data Input / Output: Data bus.
Internally Not Connected: These could be left unconnected, but it is recommended they be connected or VSS.
Data Output Power: Provide isolated power to output buffers for improved noise immunity.
Data Output Ground: Provide isolated ground to output buffers for improved noise immunity.
Power for the input buffers and core logic.
Ground for the input buffers and core logic.
I Revision 1.0
Page 4 / 39
Jun., 2013
5 Page 
A3V56S30GTP
A3V56S40GTP
256M Single Data Rate Synchronous DRAM
Truth Table
Command Truth Table
COMMAND
Symbol CKEn-1
Device deselect
No operation
Burst stop
Read
Read with auto precharge
Write
Write with auto precharge
Bank activate
Precharge select bank
Precharge all banks
Mode register set
DSL
NOP
BST
RD
RDA
WR
WRA
ACT
PRE
PALL
MRS
H
H
H
H
H
H
H
H
H
H
H
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CKEn
X
X
X
X
X
X
X
X
X
X
X
/CS
H
L
L
L
L
L
L
L
L
L
L
/RAS
X
H
H
H
H
H
H
L
L
L
L
/CAS
X
H
H
L
L
L
L
H
H
H
L
/WE
X
H
L
H
H
L
L
H
L
L
L
BA1
X
X
X
V
V
V
V
V
V
X
L
BA0
X
X
X
V
V
V
V
V
V
X
L
A10/
AP
X
X
X
L
H
L
H
V
L
H
L
A12-11,
A9 ~ A0
X
X
X
V
V
V
V
V
X
X
OP code
CKE Truth Table
Current state
Function
Activating
Enter Clock suspend or
Active power down
Clock suspend or
Maintain Clock suspend or
Active power down Active power down
Clock suspend or
Active power down
Exit Clock suspend or
Active power down
All banks idle
Auto refresh command
All banks idle
Enter Self refresh
All banks idle
Enter Precharge power down
Symbol
REF
SREF
Self refresh
Exit Self refresh
Precharge
down
power Exit Prechage power down
Precharge power Maintain Precharge power
down
down
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CKEn-1
H
H
L
L
H
H
H
H
L
L
L
L
L
CKEn
L
L
L
H
H
L
L
L
H
H
H
H
L
/CS
L
H
X
X
L
L
L
H
L
H
L
H
X
/RAS
V
X
X
X
L
L
H
X
H
X
H
X
X
/CAS
V
X
X
X
L
L
H
X
H
X
H
X
X
/WE /Address
VV
XX
XX
XX
HX
HX
HX
XX
HX
XX
HX
XX
XX
I Revision 1.0
Page 10 / 39
Jun., 2013
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet A3V56S30GTP.PDF ] | |
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