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PDF NB6L56 Data sheet ( Hoja de datos )
| Número de pieza | NB6L56 | |
| Descripción | 2.5V / 3.3V Dual 2:1 Differential Clock / Data Multiplexer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB6L56
2.5V / 3.3V Dual 2:1
Differential Clock / Data
Multiplexer with LVPECL
Outputs
Multi−Level Inputs w/ Internal Termination
The NB6L56 is a high performance Dual 2−to−1 Differential Clock
or Data multiplexer. The differential inputs incorporate internal 50 W
termination resistors that are accessed through the VT pin. This feature
allows the NB6L56 to accept various Differential logic level
standards, such as LVPECL, CML or LVDS. Outputs are 800 mV
LVPECL signals. For interface options see Figures 12 − 15.
The NB6L56 produces minimal Clock or Data jitter operating up to
2.5 GHz or 2.5 Gbps, respectively. As such, the NB6L56 is ideal for
SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The NB6L56 is offered in a low profile 5 mm x 5 mm 32−pin QFN
package and is a member of the ECLinPS MAX™ family of high
performance Clock / Data products. Application notes, models, and
support documentation are available at www.onsemi.com.
Features
• Maximum Input Data Rate > 2.5 Gbps
• Maximum Input Clock Frequency > 2.5 GHz
• Jitter
< 1 ps RMS RJ (Data)
< 10 ps PP DJ (Data)
< 0.7 ps RMS Crosstalk induced jitter (CLOCK)
• 360 ps Max Propagation Delay
• 180 ps Max Rise and Fall Times
• Operating Range:
VCC = 2.5 ± 5% (2.375 V to 2.625 V)
VCC =3.3 ± 10% (3.0 V to 3.6 V)
• Internal 50 W Input Termination Resistors
• Industrial Temp. Range (−40°C to 85°C)
• QFN−32 Package
• These are Pb−Free Devices
Applications
• Clock and Data Distribution
• Networking and Communications
• High End Computing
• Wireless and Wired Infrastructure
End Products
• Servers
• Ethernet Switch/Routers
• ATE
• Test and Measurement
http://onsemi.com
1 32
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
1
NB6L
56
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
A
B
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 0
1
Publication Order Number:
NB6L56/D
1 page  
NB6L56
Table 5. DC CHARACTERISTICS VCC = 2.5 ± 5% (2.375 V to 2.625 V); VCC = 3.3 ± 10% (3.0 V to 3.6 V) (Note 5)
Symbol
Characteristic
Min Typ Max
Unit
ICC Power Supply Current (Inputs and Outputs Open)
LVPECL OUTPUTS
65 85 mA
VOH
VOL
VOUT
Output HIGH Voltage
Output LOW Voltage
Output Swing (Single Ended)
Output Swing (Differential)
VCC – 1.145
VCC – 2.000
400
800
800
1600
VCC − 0.895
VCC − 1.695
mV
mV
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Note 6) (Figures 5 and 6)
Vth Input Threshold Reference Voltage Range
VIH Single−ended Input HIGH Voltage
VIL Single−ended Input LOW Voltage
VISE
Single−ended Input Voltage (VIH − VIL ) (Note 6)
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 7) (Figures 7 and 8)
1125
Vth + 75
GND
150
VCC − 75
VCC
Vth − 75
3015
mV
mV
mV
mV
VIHD
Differential Input HIGH Voltage
VILD
Differential Input LOW Voltage
VID Differential Input Voltage (VIHD − VILD)
VCMR
Input Common Mode Range (Differential Configuration) (Figure 9)
IIH Input HIGH Current (VTnx Open)
IIL Input LOW Current (VTnx Open)
LVTTL / LVCMOS INPUTS (SELA/SELB)
1200
GND
100
1150
−150
−150
VCC
VIHD − 100
1890
VCC − 50
150
150
mV
mV
mV
mV
mA
mA
VIH Input HIGH Voltage
VIL Input LOW Voltage
IIL Input LOW Current (VIN = 0.5 V)
IIH Input HIGH Current (VCC)
TERMINATION RESISTORS
2.0
−300
V
0.8 V
mA
75 mA
RTIN
Internal Input Termination Resistor INxn/INxn to VTxn
REFERENCE VOLTAGE
45 50 55 W
VREF−AC Output Reference Voltage
VCC − 1.35 VCC − 1.2 VCC − 1.1
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs evaluated with 50 W resistors to VTT = VCC − 2.0 V for proper operation (See Figure 16).
6. VTH is applied to the complementary input when operating in single−ended mode. VIH, VIL and VTH parameters must be complied with
simultaneously.
7. VIHD, VILD and VCMR parameters must be complied with simultaneously. VCMR max varies 1:1 with VCC.
http://onsemi.com
5
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| PDF Descargar | [ Datasheet NB6L56.PDF ] | |
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