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PDF NB3F8L3010C Data sheet ( Hoja de datos )
| Número de pieza | NB3F8L3010C | |
| Descripción | 3.3V / 2.5V / 1.8V / 1.5V 3:1:10 LVCMOS Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
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NB3F8L3010C
3.3V / 2.5V / 1.8V / 1.5V
3:1:10 LVCMOS Fanout Buffer
Description
The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDOn supplies which must be equal or less than VDD.
A Mux selects between a Crystal input, or either of two
differential/SE Clock / Data inputs. Differential Inputs accept
LVPECL, LVDS, HCSL, or SSTL and Single−Ended levels. The
MUX control lines, SEL0 and SEL1, select CLK0/CLK0,
CLK1/CLK1, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (HZ) when Low per
Table 4.
Outputs consist of 10 single−ended LVCMOS outputs.
Features
• Ten CMOS / LVTTL Outputs up to 200 MHz
• Differential Inputs Accept LVPECL, LVDS, HCSL, or SSTL
• Crystal Oscillator Interface
• Crystal Input Frequency Range: 10 MHz to 50 MHz
• Output Skew: 10 ps Typical
• Additive RMS Phase Jitter @ 125 MHz, (12 kHz – 20 MHz): 0.03 ps
(Typical)
• Synchronous Output Enable
• Output Defined Level When Input is Floating
• Power Supply Modes:
♦ Single 3.3 V
♦ Single 2.5 V
♦ Mixed 3.3 V ± 5% Core/2.5 V ± 5% Output Operating Supply
♦ Mixed 3.3 V ± 5% Core/1.8 V ± 0.2 V Output Operating Supply
♦ Mixed 3.3 V ± 5% Core/1.5 V ± 0.15 V Output Operating Supply
♦ Mixed 2.5 V ± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply
♦ Mixed 2.5 V ± 5% Core /1.5 V ± 0.15 V Output Operating Supply
• Two Separate Output Bank Power Supplies
• Industrial temp. range -40°C to 85°C
• These are Pb−Free Devices
Applications
• Clock Distribution
• Networking and Communications
• High End Computing
• Wireless and Wired Infrastructure
End Products
• Servers
• Ethernet Switch/Routers
• ATE
• Test and Measurement
www.onsemi.com
1 32
QFN32
G SUFFIX
CASE 488AM
MARKING
DIAGRAM
1
NB3F8L
3010C
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information page 12 of this
data sheet.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 7
1
Publication Order Number:
NB3F8L3010C/D
1 page  
NB3F8L3010C
Table 9. POWER SUPPLY DC CHARACTERISTICS VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5% (2.375 V to
2.625 V) and VDDOn = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ±
0.15 V (1.35 V to 1.65 V); TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
Min Typ Max Unit
IDD VDD Power Supply
Current
OE = 0, no load
3.3 V ± 5%; VDDOn = 3.3 V ± 5% or 2.5 V ± 5% or
1.8 V ± 0.2 V or 1.5 V ± 0.15 V
2.5 V ± 5%; VDDOn = 2.5 V ± 5% or 1.8 V ± 0.2 V
or 1.5 V ± 0.15 V
30 50 mA
IDDO
VDDO Power Supply
Current
OE = 0, no load
3.3 V ± 5%; VDDOn = 3.3 V ± 5% or 2.5 V ± 5% or
1.8 V ± 0.2 V or 1.5 V ± 0.15 V
2.5 V ± 5%; VDDOn = 2.5 V ± 5% or 1.8 V ± 0.2 V
or 1.5 V ± 0.15 V
5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 10. DC CHARACTERISTICS TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
Min Typ Max Unit
VIH
VIL
IIH
IIL
VOH
VOL
VPP
VIHCMR
LVCMOS / LVTTL Input High Voltage
(OE, SELx)
LVCMOS / LVTTL Input Low Voltage
(OE, SELx)
Input High Current
OE, SELx,
CLKx/CLKx
Input Low Current
OE, SELx
CLKx
CLKx
Output High Voltage (Note 4)
Output Low Voltage (Note 4)
Peak−to−Peak Input Voltage
VIL > −0.3 V
CLKx/CLKx
Input High Level Common Mode
Range
VCM = VIH; VIL > −0.3 V CLKx/CLKx
VDD = 3.3 V ±5%
VDD = 2.5 V ± 5%
VDD = 3.3 V ±5%
VDD = 2.5 V ± 5%
VDD = VIN = 3.465 V
VDD = VIN = 3.465 V or 2.625 V
VDD = 3.465 V; VIN = 0.0 V
VDD = 3.465 V or 2.625 V VIN = 0.0 V
VDD = 3.465 V or 2.625 V VIN = 0.0 V
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDDOn = 3.3 V ± 5% or 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDD = 3.3 V ±5% or VDD = 2.5 V ± 5%
VDD = 3.3 V ±5% or VDD = 2.5 V ± 5%
2
1.7
−0.3
−0.3
−5
−5
−150
2.6
1.8
1.2
0.9
0.15
0.5
VDD + 0.3
VDD + 0.3
0.8
0.7
150
150
V
V
mA
mA
V
0.5 V
0.4
0.37
1.3 V
VDD − 0.85
V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. Outputs terminated with 50 W to VDDOn/2. See Parameter Measurement Information..
Table 11. AC CHARACTERISTICS VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5% (2.375 V to 2.625 V) and
VDDOn = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V (1.35 V
to 1.65 V); TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
Min Typ Max Unit
fMAX
Output Frequency Using External
Crystal
10 50 MHz
Using External
Clock Source
(Note 5)
DC 200 MHz
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5
5 Page 
NB3F8L3010C
Differential Clock Input Interface
The CLK / CLK accept LVDS, LVPECL, SSTL, HCSL
differential signals. Signals must meet the VPP and VCMR
input requirements. Figures 9 to 13 show interface
examples for the CLK / CLK input with built−in 50 W
terminations driven by the most common driver types. The
input interfaces suggested here are examples only. If the
driver is from another vendor, use their termination
recommendation. Please consult with the vendor of the
driver component to confirm the driver termination
requirements.
VDD = +3.3 V
Qx
LVPECL
Qx
GND = 0.0 V
VDD = +3.3 V
VDD = +3.3 V
125 W
Zo = 50 W
Zo = 50 W
125 W
CLKx
Differential
CLKx
In
84 W
84 W
GND = 0.0 V
GND = 0.0 V
Figure 9. CLK / CLK Input Driven by 3.3 V LVPECL
Driver (Thevenin Parallel Termination)
VDD = +3.3 V
VDD = +3.3 V
Qx
LVPECL
Qx
Zo = 50 W
Zo = 50 W
50 W
CLKx
Differential
CLKx
In
50 W
GND = 0.0 V
50 W
GND = 0.0 V
GND = 0.0 V
Figure 10. CLK / CLK Input Driven by 3.3 V
LVPECL Driver (“Y” Parallel Termination)
VDD = +3.3 V
VDD = +3.3 V
Qx 33 W (Opt)
HCSL
Qx 33 W (Opt)
Zo = 50 W
Zo = 50 W
50 W
CLKx
Differential
CLKx
In
50 W
GND = 0.0 V
GND = 0.0 V
GND = 0.0 V
VDD = +3.3 V
Qx
LVDS
Qx
GND = 0.0 V
Zo = 50 W
Zo = 50 W
100 W
VDD = +3.3 V
CLKx
Differential
CLKx
In
GND = 0.0 V
Figure 11. CLK / CLK Input Driven by a 3.3 V
HCSL Driver
Figure 12. CLK / CLK Input Driven by 3.3 V
LVDS Driver
VDD = +2.5 V
Qx
SSTL
Qx
VDD = +2.5 V
VDD = +3.3 V
120 W
Zo = 50 W
Zo = 50 W
120 W
CLKx
Differential
CLKx
In
120 W
120 W
GND = 0.0 V
GND = 0.0 V
GND = 0.0 V
Figure 13. CLK / CLK Input Driven by 2.5 V SSTL Driver
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11
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| PDF Descargar | [ Datasheet NB3F8L3010C.PDF ] | |
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