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Número de pieza MT90810AK3
Descripción Flexible MVIP Interface Circuit
Fabricantes Zarlink Semiconductor 
Logotipo Zarlink Semiconductor Logotipo



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CMOS MT90810
Flexible MVIP Interface Circuit
Data Sheet
Features
• MVIPand ST-BUScompliant
• MVIP Enhanced Switching with 384x384 channel
capacity (256 MVIP channels; 128 local
channels)
• On-chip PLL for MVIP master/slave operation
• Local output clocks of 2.048,4.096,8.192 MHz
with programmable polarity
• Local serial interface is programmable to 2.048,
4.096 or 8.192 Mb/s with associated clock
outputs
• Additional control output stream
• Per-channel message mode
• Two independently programmable groups of up to
12 framing signals each
• Motorola non-multiplexed or Intel
multiplexed/non-multiplexed microprocessor
interface
Applications
• Medium size digital switch matrices
• MVIP interface functions
• Serial bus control and monitoring
August 2005
Ordering Information
MT90810AK3 100 Pin PQFP*
*Pb Free Sn-Bi Plating
Trays
0°C to +70°C
• Centralized voice processing systems
• Voice/Data multiplexer
Description
Zarlink’s MT90810 is a Flexible MVIP Interface Circuit
(FMIC). The MVIP (Multi-Vendor Integration Protocol)
compliant device provides a complete MVIP compliant
interface between the MVIP Bus and a wide variety of
processors, telephony interfaces and other circuits. A
built-in digital time-slot switch provides MVIP enhanced
switching between the full MVIP Bus and any
combination of up to 128 full duplex local channels of
64 kbps each. An 8 bit microprocessor port allows real-
time control of switching and programming of device
configuration. On-board clock circuitry, including both
analog and digital phase-locked loops, supports all
MVIP clock modes. The local interface supports PCM
rates of 2.048, 4.096 and 8.192 Mb/s, as well as
parallel DMA through the microprocessor port.
SEC8K
C4b
C2o
F0b
DSo[0:7]
DSi[0:7]
LDO[0:3]
LDI[0:3]
TCK
TMS
TDI
TDO
EX_8KA EX_8KB X2 X1/CLKIN PLL_LO PLL_LI FRAME
Timing and Clock Control
(Oscillator and Analog & Digital PLLs)
Enhanced Switch
S-P/ Data Memory
P-S
Connection Memory
Programmable
Framing Signals
JTAG
Microprocessor Interface
CLK2
CLK4
CLK8
RESET
CSTo
FGA[0:11]
FGB[0:11]
ERR
AD[0:7] A[0:1] ALE WR/ RD/ CS RDY/ DREQ[0:1] DACK[0:1]
R/W DS
DTACK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.

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MT90810AK3 pdf
MT90810
Data Sheet
Pin Description (continued)
Pin #
12
13
17
18
22
23
21
24
15, 40,
65, 86
16, 41,
52, 66,
79, 93
Name
TDO
TMS
X1/CLKIN
X2
PLL_LO
PLL_LI
VCO_VS
S
VCO_VD
D
VDD[0:3]
VSS[0:5]
Description
JTAG Serial Output Data (Output). If not used, this pin should be left unconnected.
JTAG Mode Control Input (TTL Input). If not used, this pin should be left unconnected.
Clock Input Pin/ Crystal Oscillator Pin1.
Crystal Oscillator Pin 2 (Input). If X1 is clock input, this pin should be left
unconnected.
PLL Loop Filter Output. (Output 6 mA drive).
PLL Loop Filter Input. (1 µA Low level/High level Input current).
Ground for On-chip VCO.
+5 Volt Power Supply for On-chip VCO.
+5 Volt Power Supply.
Ground.
Device Overview
Zarlink’s MT90810 is a MVIP compliant device. It provides a complete, cost effective, MVIP compliant interface
between the MVIP Bus and a wide variety of processors, telephony interfaces and other circuits. The FMIC
supports 384 full duplex, time division multiplexed (TDM), channels. These channels are divided into 256 full duplex
MVIP channels and 128 full duplex local channels. The sample rate for each channel is 8 kHz and the width of each
channel is 8 bits for a total data rate of 64 kbits/s per channel.
The FMIC’s internal clock circuitry includes both an analog and a digital PLL and supports all MVIP clock modes.
The device can be configured as a timing master whereby an external 16.384 MHz crystal or 4.096, 8.192 or
16.384 MHz external clock source is used to generate MVIP clock signals. The device can also operate as a slave
to the MVIP bus, synchronizing its master clock to the MVIP 4 MHz bus clock.
The device’s local serial interface supports PCM rates of 2.048, 4.096 and 8.192 Mb/s, per channel message
mode, an additional control stream, as well as parallel DMA through the microprocessor port. Furthermore, the
FMIC’s programmable group of output framing signals and local output clocks may be used to provide the
appropriate frame and clock pulses to drive other local serial buses such as GCI.
A microprocessor interface permits reading and writing of the data memory, connection memory and all internal
control registers. The Connection and Data memory can be read and updated while the MVIP bus is active, that is,
connections can be made without interrupting bus activities.
Functional Description
Switching
The FMIC provides for switching of data from any input channel to any output channel. This is accomplished by
buffering a single sample of each channel in an on-chip 384 byte static RAM. Samples are written into this data
RAM in a fixed order and read out in an order determined by the programming of the connection memory. An input
shift register and holding latch for each input stream make up the serial to parallel conversion blocks on the input of
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Zarlink Semiconductor Inc.

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MT90810AK3 arduino
MT90810
Data Sheet
0 to 7, respectively. For example, if only two DSo channels, 0 and 2 on stream 0, are enabled then the
corresponding channels 0 and 2 on FGA4 will be pulled low and the remaining channels will be left high. Similarly,
FGB4 to FGB11 outputs correspond to output drive enables for the MVIP DSi channels within streams 0 to 7,
respectively.
In mode 2, frame groups A&B are programmed as output framing pulses for use with the local serial data streams
(refer to Figure 16 - “Frame Pulse Timing for Mode 2” for further details). The position of the first framing signal in a
group is determined by an 11 bit quantity. The quantity is the FMIC state number (the number of 16 MHz clock
cycles during one frame) minus one. The lower eight bits of this quantity are located in the frame start register, and
the upper three bits are located in the frame mode register.The width of the framing signal is determined by the
state of the FRM_TYPE bit in the frame mode register and can be either a single bit cell time or 8 bit cell times. All
framing signals in the same group (A or B) follow each other sequentially, that is, the first FGx[0] is asserted then
exactly 8 bit cell times later FGx[1] is asserted and so on until the last framing signal in the group is asserted. The
distance between consecutive frame pulses within a frame group can be one 2, 4 or 8 Mb/s channel time and can
be specified by two bits in the frame mode register.
Mode 3 is identical to mode 2 except the polarity of the framing pulses is logically inverted.
Refer to Tables 13 to 16 for details on the frame start and frame mode registers.
All the framing signals FGA[0:11] and FGB[0:11] are available in the 100 pin PQFP package.
Delay through the MT90810
Switching delay through the FMIC is dependent on input and output stream, source and destination channel, as
well as, I/O data rate. A summary of throughput delay values for the device is provided in Table 1, “Throughput
Delay Values”. The minimum delay achievable in the MT90810 depends on the data rate selected for the streams.
When switching from a slower input data rate to a faster output data rate, the minimum delay is set by the faster
output data rate and the maximum delay is set by the slower input data rate. When switching from a faster input
data rate to a slower output data rate, the minimum delay is set by the slower output data rate and the maximum
delay is set by the faster input data rate.
Input - Output
Rate
Throughput Delay
min max
2.048 - 2.048 Mb/s 2 x 2 Mb/s t.s.
1 fr. + 2 x 2 Mb/s t.s.
4.096 - 4.096 Mb/s 3 x 4 Mb/s t.s.
1 fr. + 5 x 4 Mb/s t.s.
8.192 - 8.192 Mb/s 5 x 8 Mb/s t.s.
1 fr. + 11 x 8 Mb/s t.s.
2.048 - 4.096 Mb/s 3 x 4 Mb/s t.s.
1 fr. + 2 x 2 Mb/s t.s.
2.048 - 8.192 Mb/s 5 x 8 Mb/s t.s.
1 fr. + 2 x 2 Mb/s t.s.
4.096 - 2.048 Mb/s 2 x 2 Mb/s t.s.
1 fr. + 5 x 4 Mb/s t.s.
8.192 - 2.048 Mb/s 2 x 2 Mb/s t.s.
1 fr. + 11 x 8 Mb/s t.s.
Table 1 - Throughput Delay Values
t.s.=timeslot is used synonymously with channel
fr.=125 µs frame
2 Mb/s t.s.=3.9 µs
4 Mb/s t.s.=1.95 µs
8 Mb/s t.s.=0.975 µs
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