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PDF FDMS3006SDC Data sheet ( Hoja de datos )
| Número de pieza | FDMS3006SDC | |
| Descripción | N-Channel Dual Cool 56 PowerTrench SyncFET | |
| Fabricantes | Fairchild Semiconductor | |
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July 2015
FDMS3006SDC
N-Channel Dual CoolTM 56 PowerTrench® SyncFETTM
30 V, 90 A, 1.9 mΩ
Features
Dual CoolTM Top Side Cooling PQFN package
Max rDS(on) = 1.9 mΩ at VGS = 10 V, ID = 30 A
Max rDS(on) = 2.7 mΩ at VGS = 4.5 V, ID = 26 A
High performance technology for extremely low rDS(on)
SyncFET Schottky Body Diode
RoHS Compliant
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process.
Advancements in both silicon and Dual CoolTM package
technologies have been combined to offer the lowest rDS(on)
while maintaining excellent switching performance by extremely
low Junction-to-Ambient thermal resistance. This device has the
added benefit of an efficient monolithic Schottky body diode.
Applications
Synchronous Rectifier for DC/DC Converters
Telecom Secondary Side Rectification
High End Server/Workstation Vcore Low Side
Pin 1
S
SS
G
S
S
D
D
D
D
D
D
Top
Dual CoolTM 56
Bottom
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
ID
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
TC = 25 °C
TC = 25 °C
TA = 25 °C
EAS
dv/dt
Single Pulse Avalanche Energy
Peak Diode Recovery dv/dt
PD
TJ, TSTG
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
S
G
(Note 4)
(Note 1a)
(Note 3)
(Note 5)
(Note 1a)
RθJC
RθJC
RθJA
RθJA
RθJA
RθJA
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Top Source)
(Bottom Drain)
(Note 1a)
(Note 1b)
(Note 1i)
(Note 1j)
(Note 1k)
Device Marking
3006S
Device
FDMS3006SDC
Package
Dual CoolTM 56
Reel Size
13’’
Ratings
30
±20
90
179
34
200
144
1.8
89
3.3
-55 to +150
2.7
1.4
38
81
16
23
11
Tape Width
12 mm
D
D
Units
V
V
A
mJ
V/ns
W
°C
°C/W
Quantity
3000 units
©2012 Fairchild Semiconductor Corporation
FDMS3006SDC Rev.1.5
1
www.fairchildsemi.com
1 page  
Typical Characteristics TJ = 25 °C unless otherwise noted
10
ID = 30 A
8
6
4
VDD = 10 V
VDD = 15 V
VDD = 20 V
2
0 0 20 40
Qg, GATE CHARGE (nC)
60
Figure 7. Gate Charge Characteristics
6000
1000
Ciss
Coss
100
Crss
f = 1 MHz
VGS = 0 V
100.1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. CapacitancevsDrain
to Source Voltage
50
10 TJ = 25 oC
TJ = 100 oC
TJ = 125 oC
200
RθJC = 1.4 oC/W
150
VGS = 10 V
VGS = 4.5 V
100
Limited by Package
50
1
0.01
0.1 1 10
tAV, TIME IN AVALANCHE (ms)
100
Figure9. UnclampedInductive
Switching Capability
500
300
100 100 μs
10
THIS AREA IS
1 LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
0.1 RθJA = 81 oC/W
TA = 25 oC
1 ms
10 ms
100 ms
1s
10 s
DC
0.01
0.01 0.1 1 10 100200
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
0
25 50 75 100 125
Tc, CASE TEMPERATURE (oC)
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
150
5000
1000
100
10 SINGLE PULSE
RθJA = 81 oC/W
TA = 25 oC
1
10-4 10-3 10-2
10-1
1
10
t, PULSE WIDTH (sec)
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2012 Fairchild Semiconductor Corporation
FDMS3006SDC Rev.1.5
5
www.fairchildsemi.com
5 Page | ||
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| PDF Descargar | [ Datasheet FDMS3006SDC.PDF ] | |
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