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PDF 25Q80BV Data sheet ( Hoja de datos )
| Número de pieza | 25Q80BV | |
| Descripción | W25Q80BV | |
| Fabricantes | Winbond | |
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W25Q80BV
8M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
Publication Release Date: May 23, 2014
- 1 - Revision J
1 page  
W25Q80BV
1. GENERAL DESCRIPTION
The W25Q80BV (8M-bit) Serial Flash memory provides a storage solution for systems with limited space,
pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
and storing voice, text and data. The device operates on a single 2.5V to 3.6V power supply with current
consumption as low as 4mA active and 1µA for power-down.
The W25Q80BV array is organized into 4,096 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q80BV
has 256 erasable sectors and 16 erasable blocks respectively. The small 4KB sectors allow for greater
flexibility in applications that require data and parameter storage. (See figure 2.)
The W25Q80BV supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1
(DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing
equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O
when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true
XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array
control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer
and device identification with a 64-bit Unique Serial Number.
2. FEATURES
Family of SpiFlash Memories
– W25Q80BV: 8M-bit/1M-byte (1,048,576)
– 256-byte per programmable page
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
Highest Performance Serial Flash
– 104MHz Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/S continuous data transfer rate
– Up to 8X that of ordinary Serial Flash
– More than 100,000 erase/program cycles(1)
– More than 20-year data retention
Efficient “Continuous Read Mode”
– Low Instruction overhead
– Continuous Read with 8/16/32/64-Byte Wrap
– As few as 8 clocks to address memory
– Allows true XIP (execute in place) operation
– Outperforms X16 Parallel Flash
Low Power, Wide Temperature Range
– Single 2.5 to 3.6V supply
– 4mA active current, <1µA Power-down current
– -40°C to +85°C operating range
Flexible Architecture with 4KB sectors
– Uniform Sector/Block Erase (4/32/64K-bytes)
– Program one to 256 bytes
– Erase/Program Suspend & Resume
Advanced Security Features
– Software and Hardware Write-Protect
– Top/Bottom, 4KB complement array protection
– Lock-Down and OTP array protection
– 64-Bit Unique Serial Number for each device
– Discoverable Parameters (SFDP) Register
– 3X256-Byte Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits
Space Efficient Packaging(1)
– 8-pin SOIC 150/208-mil
– 8-pad USON 2x3-mm
– 8-pad WSON 6x5-mm
– 8-pin PDIP 300-mil
– Contact Winbond for KGD and other options
Note 1. Some package types are special orders, please contact Winbond for ordering information.
Publication Release Date: May 23, 2014
- 5 - Revision J
5 Page 
W25Q80BV
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
Select (/CS) signal should be kept active low for the full duration of the /HOLD operation to avoid resetting
the internal logic state of the device.
5.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q80BV
provides several means to protect the data from inadvertent writes.
5.2.1 Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Status Register
Write Protection using Power-down instruction
Lock Down write protection until next power-up
One Time Program (OTP) write protection*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q80BV will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 38). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-
disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC,TB, BP2, BP1 and BP0) bits.
These settings allow a portion as small as 4KB sector or the entire memory array to be configured as
read only. Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be
enabled or disabled under hardware control. See Status Register section for further information.
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are
ignored except for the Release Power-down instruction.
- 11 -
Publication Release Date: May 23, 2014
Revision J
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 25Q80BV.PDF ] | |
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