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PDF WD90C00 Data sheet ( Hoja de datos )

Número de pieza WD90C00
Descripción VGA Controller
Fabricantes Western Digital 
Logotipo Western Digital Logotipo



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WD90C00 pdf
INTRODUCTION
1.0 INTRODUCTION
Many applications require greater graphics
capability than is available through the IBM
Monochrome Display Adapter (MDA), Color
Graphics Adapter (CGA), Enhanced Graphics
Adapter (EGA), Multi Color Graphics Array
(MCGA), and the Video Graphics Array (VGA).
The WDI WD90COO is a 1.25 micron, 15,000
gate CMOS VLSI device that fulfills this need and
allows for the design of very high performance
VGA graphics subsystems that are able to inter-
face with the PC/AT Bus, as well as the IBM
Micro Channel Bus, while maintaining backwards
compatibility with previous video standards.
A major advantage of using the WD90COO is that
designs implementing this graphics controller will
be able to run applications requiring MDA, CGA,
EGA, Hercules graphics, AT&T (640 by 400
graphics mode), VGA hardware and BIOS level
compatibility on analog and TTL monitors. In ad-
dition, it includes full support for running ex-
tended high resolution 1024 by 768 by 16 colors
interlaced graphics mode on 8514 Color Dis-
plays. A Noninterlaced 1024 by 768 by 16 colors
graphics mode requires external circuitry along
with a 56 MHz MCLK and 80 ns DRAMs.
1.1 FEATURES
• Provides single chip Video Graphics
Solution for IBM PC/XT/AT and Personal
System/2 compatible systems
• 100% hardware compatible with IBM'sVGA
card in all modes
• 100% EGA, CGA, MDA, Hercules Graphics,
AT&T Model 6300 compatible
• Integrated bus interface for PC/XT/AT, and
Micro Channel
• 800 by 600 x 16 colors, 640 by 400 x 256
colors
• 640 by 480 x 256 colors (512 Kbytes DRAM)
• 800 by 600 x 256 colors (512 Kbytes DRAM)
• 1024 by 768 x 16 colors interlaced graphics
mode support - 8514 monitor compatible
WD90COO
• 1024 by 768 x 16 colors noninterlaced with
external logic
• 132 column text modes, with 25, 43, or 50
rows
• Up to four simultaneous displayable fonts
• Special register locking for flat panel
applications
• Lockable palette, RAMDAC, and overscan
registers
• Display memory offset registers to control 4
Kbyte windows or 64 Kbyte windows
• Provides adapter video BIOS ROM
decoding
• True 7,8, g, 10, and 16 pixel wide fonts
• Supports up to 1 Mbyte display memory
addressing
• Load up to 16 fonts
• Special underlining in color text mode
• Two additional bits for a total of 18 address
bits for cursor location and start address
• Special double scanning
• Special display enable or blanking output
signal
• Special border disable
• Page mode addressing for CRTC refresh
cycles
• High performance FIFO memory
architecture
• Includes 8- or 16-bit wide CPU data bus
• Support for external color lookup table
(Palette Chip) with 256K available colors
• Pin for pin compatible with the PVGA1A (AT
bus mode)
• Enhanced virtual VGA support
• Up to 45 MHz maximum video clock rate
• Up to 56 MHz maximum memory clock rate
• 1.25 micron CMOS VLSI technology
• 100-pin Plastic Leadless Chip Carrier
(PLCC) or Plastic Quad Flat Pack (PQFP)
JEDEC package
• Minimizes circuit board space requirements
and lowers system cost
II
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WD90C00 arduino
WD90COO INTERFACES
WD90COO
3.2.1 DRAM Cycle Types
The WD90COO will do standard RAS/CAS single
cycle accesses to the DRAM during CPU writes
and reads in graphics modes and alphanumeric
modes. For CRTC display refresh cycles, the
WD90COO will do page mode access reads for all
cycles in graphics modes. It will also do page
mode reads to the DRAM when selected to do so
to increase performance in alphanumeric modes.
The default mode of DRAM access in al-
phanumeric mode is the standard single
RAS/CAS cycle. The WD90COO provides the
necessary control signals and address/data lines
to access the video memory as two 16 bit data in-
terleaved banks. The WD90COO will also refresh
the DRAMs with 3 or 5 refresh cycles after every
horizontal scan line.
3.3 VIDEO AND RAMDAC INTERFACE
3.3.1 RAMDAC
The WD90COO is designed to connect to an
analog CRT monitor through an external RAM-
DAC, but it may also be used to drive other types
of displays such as TTL monitors along with the
correct register programming and clocks. All the
necessary signals to interface to the video RAM-
DAC are provided.
The video interface for a CRT is very dependent
on the CRT requirements and the resolution and
depth (bits/pixels) of the image desired. New
monitors, such as multifrequency monitors, are
less stringent because of the many sync frequen-
cies available. The WD90COO can be
programmed to directly generate all the CRT sig-
nals for up to 8 bits/pixel (256 color). In addition,
external hardware can be added to allow higher
display resolutions by trading off the number of
bits/pixel such as a 1024 by 768 noninterlaced
mode.
The Micro Channel Auxiliary Video Connector
and the AT Feature Connector can be connected
to the WD90COO. The WD90COO also provides
an input for a monitor type detection interface as
done on the IBM VGA using comparators.
3.4 CLOCK INTERFACE
The WD90COO has four clock input signal pins.
These are: separate memory clock, MCLK,
which drives the DRAM timing in graphics and
alpha modes; and the three video clocks, VCLKO,
VCLK1, and VCLK2, which drive the video
timing. WD90COO also provides the option to ex-
ternally control a multiplexer that supplies the
video clock. The MCLK can also be selected as
the video dot clock.
3.5 WD90COO POWER-UP
CONFIGURATION
The WD90COO uses the memory data pins that
are "strapped" to ground or Vcc through resistors
to configure an internal configuration register
upon powerup/reset. CNF(2) will determine
whether the WD90COO will operate in AT or Micro
Channel Architecture (MCA) implementation.
Other CNF bits configured by WD90COO at
power-up/reset are used as status bits, or for
clock source control. For more information on
WD90COO power-up configuration, refer to the
PR Register section of this data sheet.
10-25-90
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