PDF FSA1256L8X Datasheet ( Hoja de datos )

Número de pieza FSA1256L8X
Descripción Low RON Low Voltage Dual SPST Analog Switch
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo

Total 9 Páginas
FSA1256L8X Hoja de datos, Descripción, Manual
March 2004
Revised January 2005
FSA1256 FSA1257 FSA1258
Low RON Low Voltage Dual SPST Analog Switch
General Description
The FSA1256, FSA1257, and FSA1258 are high perfor-
mance dual Single Pole/Single Throw (SPST) analog
switches. These devices feature ultra low RON of 1.1
maximum at 4.5V VCC and will operate over the wide VCC
range of 1.65V to 5.5V. These devices are fabricated with
sub-micron CMOS technology to achieve fast switching
speeds and are designed for break-before-make operation.
The select input is TTL level compatible. The FSA1256 fea-
tures two Normally Open (NO) switches. The FSA1257
features two Normally Closed (NC) switches. The
FSA1258 has one NO switch and one NC switch.
s Maximum 1.1On Resistance (RON) for 4.5V supply
s 0.4max RON flatness for 4.5V supply
s Space saving Pb-Free MicroPakpackaging
s Broad VCC operating range: 1.65V to 5.5V
s Fast turn-on and turn-off time
s FSA1258 features break-before-make enable circuitry
s Over-voltage tolerant TTL compatible control input
Ordering Code:
Package Code
Package Description
Number Top Mark
EB Pb-Free 8-Lead MicroPak, 1.6 mm Wide
EC Pb-Free 8-Lead MicroPak, 1.6 mm Wide
ED Pb-Free 8-Lead MicroPak, 1.6 mm Wide
Pb-Free package per JEDEC J-STD-020B.
Analog Symbols
Supplied As
5K Units on Tape and Reel
5K Units on Tape and Reel
5K Units on Tape and Reel
(Top Through View)
Truth Tables
Control Input(s)
L Disconnect
H A Connected to B
H = HIGH Logic Level
L = LOW Logic Level
MicroPakis a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation DS500883
(Top Through View)
Control Input(s)
L A Connected to B
H Disconnect

1 page

FSA1256L8X pdf
AC Loading and Waveforms
CL includes Fixture and Stray Capacitance
Logic Input Waveforms Inverted
for Switches that have the Opposite Logic Sense
FIGURE 1. Turn-On/Turn-Off Timing
FIGURE 2. Break-Before-Make Timing
FIGURE 3. OFF Isolation

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