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PDF STK672-600 Data sheet ( Hoja de datos )
| Número de pieza | STK672-600 | |
| Descripción | 2-phase Stepping Motor Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Ordering number : ENA0755A
STK672-600
Thick-Film Hybrid IC
2-phase Stepping Motor Driver
http://onsemi.com
Overview
The STK672-600 is a hybrid IC for use as a unipolar, 2-phase stepping motor driver with PWM current control.
Applications
• Office photocopiers, printers, etc.
Features
• The motor speed can be controlled by the frequency of an external clock signal.
• 2-phase excitation or 1-2 phase excitation is selected according to switching the state of the MODE1 pin (low or high).
• The excitation mode is set at the rising edge of the clock signal when the MODE2 pin is high, or at the rising edge or
falling edge when the MODE2 pin is low.
• The phase is maintained even if the excitation mode is switched in the middle of operation.
• The direction of rotation can be changed by applying a high or low signal to the CWB pin used to select the direction
of rotation.
• Supports schmitt input for 2.5V high level input.
• Incorporating a current detection resistor (0.141Ω: resistor tolerance ±2%), motor current can be set using two
external resistors.
• Equipped with an ENABLE pin that, during clock input, allows motor output to be cut-off and resumed later while
maintaining the same excitation timing.
Semiconductor Components Industries, LLC, 2013
June, 2013
62911HKPC 018-08-0102/71608HKIM No. A0755-1/19
1 page  
Precautions
STK672-600
[Damage to the internal MOSFET]
• The RESETB pin must be fixed low when applying 5V power. If the RESETB pin is allowed to go high at the same
time as the 5V power, simultaneous ON of the output phase will result, causing damage to the internal MOSFET.
[GND wiring]
• To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to
Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to Pin 18
(S.G) used to set the current and to the point where P.G1 and P.G2 share a connection.
• If the driver region VSS pin (Pin 16), S.G pin (Pin 18), P.G1 pin (Pin 2), and P.G2 pin (Pin 6) cannot be connected
to a single ground, make sure to connect the VSS pin to the control system S.GND, and the S.G pin to the P.G1 pin
and P.G2 pin.
[Input pins]
• If VDD is not being applied to the hybrid IC, do not apply voltage to input Pins 10, 12, 13, 14, 15, or 17. In addition,
if VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to VSS, Pin 16,
and do not apply a voltage greater than or equal to VDD voltage.
• Do not wire by connecting the circuit pattern on the P.C.B side to Pins 7, 8, or 11 on the N.C. shown in the internal
block diagram.
• Insert resistor RO3 (47 to 100Ω) so that the discharge energy from capacitor CO4 is not directly applied to the CMOS
IC in this hybrid device. If the diode D1 has Vf characteristics with Vf less than or equal to 0.6V (when If = 0.1A),
this will be smaller than the CMOS IC input pin diode Vf. If this is the case RO3 may be replaced with a short without
problem.
• Both TTL and CMOS levels are used for the pin 10, 12, 13, 15 and 17 inputs.
• Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 15, and 17 are
used as inputs, a 1 to 15kΩ pull-up resistor (to VDD) must be used.
At this time, use a device for the open collector driver that has output current specifications that pull the voltage down
to less than 0.6V at Low level (less than 0.6V at Low level when IOL=5mA).
• If input pins are connected to GND (VSS) using a pull-down resistor, be sure to mount a resistor having a resistance
of 120Ω or less. If designs call for a pull-down resistor having a resistance in the range 120Ω to 30kΩ, be absolutely
sure to mount a 1,000pF capacitor between the input pins and the VSS Pin. Because sufficient VIL cannot be
maintained due to the effect of input leak current, IIL=±10μA max, do not connect a pull-down resistor having a
resistance of 30kΩ or higher.
• The sample application circuit includes a simple reset circuit using D1, R03, C02, and R04. If 5V power rises while
voltage still remains in C02, the reset signal cannot be detected as LOW and the driver may be damaged because ON
operations result at the same time that driver output is in A or AB phase or B or BB phase. The voltage of C02 must
therefore be less than 0.6V when the 5V power rises.
In addition, if a RESETB signal is to be input based on an external signal such as the CLOCK signal, RESETB must
always be fixed to a Low level when the 5V power signal rises.
• To prevent malfunction due to chopping noise, we recommend that you mount a 1000pF capacitor between Pin 16 and
each of the input Pins 10, 12, 13, 14, 15, and 17. Be sure to mount the capacitor as close as possible to the pins of
hybrid IC.
If input is fixed Low, directly connect to Pin 16.
If input is fixed High, directly connect to the 5V power line.
[Current setting Vref]
• Considering the specifications of the Vref input bias current, IIB, a value of 1kΩ or less is recommended for R02.
• If the motor current is temporarily reduced, the circuit given below (STK672-600: IOH>0.2A, STK672-610:
IOH>0.3A) is recommended.
• Although the driver is equipped with a fixed current control function, it is not equipped with an overcurrent protection
function to ensure that the current does not exceed the maximum output current, IOH max. If Vref is mistakenly set to
a voltage that exceeds IOH max, the driver will be damaged by overcurrent.
No. A0755-5/19
5 Page 
Usage Notes
STK672-600
1. STK672-600 and STK672-610 input signal functions and timing
(All inputs have no internal pull-up resistor and are TTL level Schmitt trigger inputs.)
[RESETB and CLOCK (Input signal timing when power is first applied)]
As shown in the timing chart, a RESETB signal input is required by the driver to operate with the timing in which the
F1 gate is turned on first. The RESETB signal timing must be set up to have a width of at least 10μs, as shown below.
The capacitor CO2, and the resistors RO3 and RO4 in the application circuit form simple reset circuit that uses the
RC time constant rising time. However, when designing the RESETB input based on VIH levels, the application
must have the timing shown in figure.
Rise of the 5V supply
voltage
RESETB signal input
CLOCK signal
At least 10μs
At least 5μs
RESETB and CLOCK Signals Input Timing
[CLOCK (Phase switching clock)]
• Input frequency: DC to 50kHz
• Minimum pulse width: 10μs
• MODE2=1(High) Signals are read on the rising edge.
• MODE2=0(Low) Signals are read on the rising and falling edges.
[CWB (Motor direction setting)]
The direction of rotation is switched by setting CWB to 1 (high) or 0 (low). See the timing charts for details on the
operation of the outputs.
Note: The state of the CWB input must not be changed during the 6.25μs period before and after the rising edge of
the CLOCK input.
[ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and hybrid IC internal operation)]
ENABLE=1: Normal operation
ENABLE=0: Outputs A, AB, B, and BB forced to the off state.
If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 and then is later
restored to the 1 state, the IC will resume operation with the excitation timing continued from before
the point ENABLE was set to 0.
If sudden stop is applied to the CLOCK signal used for motor rotation, the motor axis may advance beyond the
theoretical position due to inertia. To stop at the theoretical position, the SLOW DOWN setting for gradually slowing
the CLOCK cycle is required.
Enable must be initially set high for input as shown in the timing chart.
[MODE1 and MODE2 (Excitation mode selection)]
MODE1=0: 2-phase excitation
MODE2=1: Rising edge of CLOCK
MODE1=1: 1-2 phase excitation
MODE2=0: Rising and falling edges of CLOCK
See the timing charts for details on output operation in these modes.
Note: The state of the MODE input must not be changed during the 5μs period before and after the rising edge of the
CLOCK input.
No. A0755-11/19
11 Page | ||
| Páginas | Total 19 Páginas | |
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