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PDF TC74VHC174FK Data sheet ( Hoja de datos )

Número de pieza TC74VHC174FK
Descripción Hex D-Type Flip Flop with Clear
Fabricantes Toshiba 
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TC74VHC174F/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC174F,TC74VHC174FT,TC74VHC174FK
Hex D-Type Flip Flop with Clear
The TC74VHC174 is an advanced high speed CMOS HEX
D-TYPE FLIP FLOP fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
Information signals applied to D inputs are transferred to the
Q output on the positive going edge of the clock pulse.
When the CLR input is held low, the Q output are in the low
logic level independent of the other inputs.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
High speed: fmax = 175 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 to 5.5 V
Low noise: VOLP = 0.8 V (max)
Pin and function compatible with 74ALS174
TC74VHC174F
TC74VHC174FT
TC74VHC174FK
Weight
SOP16-P-300-1.27A
TSSOP16-P-0044-0.65A
VSSOP16-P-0030-0.50
: 0.18 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
1 2012-02-29

1 page




TC74VHC174FK pdf
TC74VHC174F/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Symbol
Propagation delay
time
(CK-Q)
tpLH
tpHL
Propagation delay
time
( CLR -Q)
tpHL
Maximum clock
frequency
fmax
Output to output skew
Input capacitance
Power dissipation
capacitance
tosLH
tosHL
CIN
CPD
Test Condition
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
(Note 1)
5.5 ± 0.5
CL (pF)
15
50
15
50
15
50
15
50
15
50
15
50
50
50
Ta = 25°C
Min Typ. Max
7.2 11.0
9.7 14.5
4.9 7.2
6.4 9.2
7.4 11.4
9.9 14.9
5.1 7.6
6.6 9.6
95 150
55 85
130 175
90 120
― ― 1.5
― ― 1.0
4 10
(Note 2) 29
Ta = 40 to
85°C
Min Max
1.0 13.0
1.0 16.5
1.0 8.5
1.0 10.5
1.0 13.5
1.0 17.0
1.0 9.0
1.0 11.0
80
50
110
80
1.5
1.0
10
――
Unit
ns
ns
MHz
ns
pF
pF
Note 1: Parameter guaranteed by design.
tosLH = |tpLHm tpLHn|, tosHL = |tpHLm tpHLn|
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/6 (per F/F)
And the total CPD when n pcs. of flip flop operate can be gained by the following equation:
CPD (total) = 19 + 10·n
Noise Characteristics (input: tr = tf = 3 ns)
Characteristics
Symbol
Test Condition
Quiet output maximum dynamic VOL
Quiet output minimum dynamic VOL
Minimum high level dynamic input voltage
Maximum low level dynamic input voltage
VOLP
VOLV
VIHD
VILD
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
VCC (V)
5.0
5.0
5.0
5.0
Ta = 25°C
Typ. Max
0.4 0.8
0.4 0.8
3.5
1.5
Unit
V
V
V
V
5 2012-02-29

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