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PDF TC74VHC138FK Data sheet ( Hoja de datos )
| Número de pieza | TC74VHC138FK | |
| Descripción | 3-TO-8 LINE DECODOR | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TC74VHC138F/FN/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC138F,TC74VHC138FN,TC74VHC138FT,TC74VHC138FK
3-to-8 Line Decoder
The TC74VHC138 is an advanced high speed CMOS 3-to-8
DECODER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
When the device is enabled, 3 Binary Select inputs (A, B and
C) determine which one of the outputs ( Y0 - Y7 ) will go low.
When enable input G1 is held low or either G2A or G2B is held
high, decoding function is inhibited and all outputs go high.
G1, G2A , and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
• High speed: tpd = 5.7 ns (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Power down protection is provided on all inputs.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 V to 5.5 V
• Pin and function compatible with 74ALS138
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74VHC138F
TC74VHC138FN
TC74VHC138FT
TC74VHC138FK
Weight
SOP16-P-300-1.27A
SOL16-P-150-1.27
TSSOP16-P-0044-0.65A
VSSOP16-P-0030-0.50
: 0.18 g (typ.)
: 0.13 g (typ.)
: 0.06 g (typ.)
: 0.02 g (typ.)
1 2007-10-01
1 page  
TC74VHC138F/FN/FT/FK
AC Characteristics (input: tr = tf = 3 ns)
Characteristics
Propagation delay
time
(A, B, C- Y )
Symbol
tpLH
tpHL
Propagation delay
time
(G1- Y )
tpLH
tpHL
Propagation delay
time
( G2 - Y )
Input capacitance
Power dissipation
capacitance
tpLH
tpHL
CIN
CPD
Test Condition
VCC (V) CL (pF)
15
3.3 ± 0.3
50
⎯
15
5.0 ± 0.5
50
15
3.3 ± 0.3
50
⎯
15
5.0 ± 0.5
50
15
3.3 ± 0.3
50
⎯
15
5.0 ± 0.5
50
⎯
(Note)
Ta = 25°C
Ta = −40 to 85°C
Unit
Min Typ. Max Min Max
⎯ 8.2 11.4 1.0 13.5
⎯ 10.0 15.8 1.0 18.0
ns
⎯ 5.7 8.1 1.0 9.5
⎯ 7.2 10.1 1.0 11.5
⎯ 8.1 12.8 1.0 15.0
⎯ 10.6 16.3 1.0 18.5
ns
⎯ 5.6 8.1 1.0 9.5
⎯ 7.1 10.1 1.0 11.5
⎯ 8.2 11.4 1.0 13.5
⎯ 10.7 14.9 1.0 17.0
ns
⎯ 5.8 8.1 1.0 9.5
⎯ 7.3 10.1 1.0 11.5
⎯ 4 10 ⎯ 10 pF
⎯ 34 ⎯ ⎯ ⎯ pF
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC
Input Equivalent Circuit
INPUT
5 2007-10-01
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet TC74VHC138FK.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TC74VHC138F | 3-TO-8 LINE DECODOR | Toshiba |
| TC74VHC138FK | 3-TO-8 LINE DECODOR | Toshiba |
| TC74VHC138FN | 3-TO-8 LINE DECODOR | Toshiba |
| TC74VHC138FS | 3-TO-8 LINE DECODOR | Toshiba |
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