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PDF W12NK95Z Data sheet ( Hoja de datos )

Número de pieza W12NK95Z
Descripción STW12NK95Z
Fabricantes STMicroelectronics 
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W12NK95Z Hoja de datos, Descripción, Manual
STW11NK100Z
STW12NK95Z
N-channel 950V - 0.69- 10A - TO-247
Zener - Protected SuperMESH™ PowerMOSFET
General features
www.DataSheet4U.com Type
VDSS
(@Tjmax)
RDS(on)
ID
PW
STW12NK95Z 950 V < 0.9010 A 230W
Gate charge minimized
100% avalanche tested
Extremely high dv/dt capability
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Applications
Switching application
TO-247
Internal schematic diagram
Order codes
Part number
STW12NK95Z
Marking
W12NK95Z
Package
TO-247
Packaging
Tube
August 2006
Rev 2
1/14
www.st.com
14

1 page

W12NK95Z pdf
STW12NK95Z
2 Electrical characteristics
Electrical characteristics
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(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
ID = 1mA, VGS= 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating,
Tc = 125°C
IGSS
VGS(th)
RDS(on)
Gate body leakage current
(VGS = 0)
VGS = ± 20V
Gate threshold voltage
VDS = VGS, ID = 100µA
Static drain-source on
resistance
VGS = 10V, ID = 5 A
Min. Typ. Max. Unit
950 V
1 µA
50 µA
±10 µA
3 3.75 4.5 V
0.69 0.9
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1)
Ciss
Coss
Crss
Forward transconductance VDS =15V, ID = 5A
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25V, f=1 MHz, VGS=0
12
3500
280
58
S
pF
pF
pF
Cosseq(2).
Equivalent output
capacitance
VGS=0, VDS =0V to 760V
117
pF
Qg Total gate charge
Qgs Gate-source charge
Qgd Gate-drain charge
VDD=760V, ID = 10A
VGS =10V
(see Figure 15)
113 nC
19 152 nC
60 nC
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
Table 7. Switching times
Symbol
Parameter
td(on)
tr
Turn-on Delay Time
Rise Time
td(off)
tf
Turn-off Delay Time
Fall Time
Test conditions
VDD=475V, ID=5A,
RG=4.7Ω, VGS=10V
(see Figure 14)
VDD=475V, ID=5A,
RG=4.7Ω, VGS=10V
(see Figure 14)
Min. Typ. Max. Unit
31 ns
20 ns
88 ns
55 ns
5/14

5 Page

W12NK95Z arduino
STW12NK95Z
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
www.DataSheet4U.com
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