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PDF TH58NVG3D4BTG00 Data sheet ( Hoja de datos )
| Número de pieza | TH58NVG3D4BTG00 | |
| Descripción | 8 GBIT (1024M x 8 BIT) CMOS NAND E2PROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA CONFIDENTIAL
TH58NVG3D4BTG00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
8 GBIT (1024M × 8 BIT) CMOS NAND E2PROM (Multi Level Cell)
Lead-Free
DESCRIPTION
The TH58NVG3D4B is a single 3.3 V 8 Gbit (8,858,370,048 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 128 pages × 4096blocks.
The device has a 2112-byte static register which allow program and read data to be transferred between the
register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block
unit (256 Kbytes + 8 Kbytes: 2112 bytes × 128 pages).
The TH58NVG3D4B is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell array
Register
Page size
Block size
TH58NVG3D4B
2112 × 256K × 8 × 2
2112 × 8
2112 bytes
(256K + 8K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Max 4096 blocks
Min 3936 blocks
• Power supply
VCC = 2.7 V to 3.6 V
• Program/Erase Cycles
10000 Cycles (With 4bit/528Byte ECC)
• Access time
Cell array to register 50 µs max
Serial Read Cycle
50 ns min
• Program/Erase time
Auto Page Program
Auto Block Erase
800 µs/page typ.
3 ms/block typ.
• Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
10 mA typ.
10 mA typ.
10 mA typ.
100 µA max
• Package
TH58NVG3D4BTG00 TSOP I 48-P-1220-0.50
(Weight: 0.53 g typ.)
• Lead-Free
1 2004-09-03A
1 page  
TOSHIBA CONFIDENTIAL
TH58NVG3D4BTG00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70 , VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
tCLS
tCLH
tCS
tCH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tWW
tRR
tRW
tRP
tRC
tREA
tCEA
tCLEA
tALEA
tOH
tRHZ
tCHZ
tREH
tIR
tRHW
tWHC
tWHR
tR
tWB
tRST
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Ready to WE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time
CE Access Time
CLE Access Time
ALE Access Time
Data Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
Output-High-impedance-to- RE Falling Edge
RE High to WE Low
WE High to CE Low
WE High to RE Low
Memory Cell Array to Starting Address
WE High to Busy
Device Reset Time (Ready/Read/Program/Erase)
MIN
MAX
UNIT
0
10
0
10
25
0
10
20
10
50
15
100
20
20
35
50
35
45
45
45
10
30
20
15
0
30
30
30
50
200
6/6/10/500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
NOTES
5 2004-09-03A
5 Page 
TOSHIBA CONFIDENTIAL
Column Address Change in Read Cycle Timing Diagram (1/2)
TH58NVG3D4BTG00
CLE
CE
tCLS tCLH
tCS tCH
WE
tWC
tCLS tCLH
tCS tCH
tCLEA
tCEA
tALH tALS
tALH
tALS
ALE
RE
tDS tDH
tR
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
tWB
tDS tDH
tRC
tRR tREA
I/O
RY / BY
00h
CA0 CA8 PA0 PA8 PA16
to 7
to 11
to 7
to 15
to 18
30h
Column address
A
Page address
P
DOUT DOUT DOUT
A A+1 A+N
Page address
P
Column address
A
1
Continues from 1 of next page
11 2004-09-03A
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TH58NVG3D4BTG00.PDF ] | |
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