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PDF CAT93C56 Data sheet ( Hoja de datos )

Número de pieza CAT93C56
Descripción 2Kb Microwire Serial EEPROM
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CAT93C56, CAT93C57
2-Kb Microwire Serial
CMOS EEPROM
CAT93C57 Not Recommended for New
Designs: Replace with CAT93C56
Description
The CAT93C56/57 is a 2−kb CMOS Serial EEPROM device which
is organized as either 128 registers of 16 bits (ORG pin at VCC) or 256
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The CAT93C56/57 features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
High Speed Operation: 2 MHz
1.8 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Sequential Read
Software Write Protection
Power−up Inadvertent Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
VCC
ORG
CS
SK
DI
CAT93C56
CAT93C57
DO
GND
Figure 1. Functional Symbol
NOTE: When the ORG pin is connected to VCC, the x16 organization is selected.
When it is connected to ground, the x8 pin is selected. If the ORG pin is left
unconnected, then an internal pullup device will select the x16 organization.
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SOIC−8
V or W SUFFIX
CASE 751BD
SOIC−8 EIAJ
X SUFFIX
CASE 751BE
TDFN−8
VP2 SUFFIX
CASE 511AK
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS
CS 1
SK 2
DI 3
DO 4
8 VCC
7 NC
6 ORG
5 GND
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2)
NC 1
VCC 2
CS 3
SK 4
8 ORG
7 GND
6 DO
5 DI
SOIC (W*)
* SOIC (W) rotated pin−out package
not recommended for new designs
Pin Name
CS
SK
DI
DO
VCC
GND
ORG
NC
PIN FUNCTION
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 19
1
Publication Order Number:
CAT93C56/D

1 page




CAT93C56 pdf
CAT93C56, CAT93C57
Table 9. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
Device Operation
The CAT93C56/57 is a 2048−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C56/57 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 10−bit
instructions for 93C57 or seven 11−bit instructions for
93C56 control the reading, writing and erase operations of
the device. When organized as X8, seven 11−bit instructions
for 93C57 or seven 12−bit instructions for 93C56 control the
reading, writing and erase operations of the device. The
CAT93C56/57 operates on a single power supply and will
generate on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 VCC to 0.7 VCC
0.5 VCC
4.5 V v VCC v 5.5 V
4.5 V v VCC v 5.5 V
1.8 V v VCC v 4.5 V
1.8 V v VCC v 4.5 V
Current Source IOLmax/IOHmax; CL=100 pF
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
tSKHI
tSKLOW
tCSH
SK
tDIS tDIH
DI VALID
VALID
tCSS
CS
tDIS
tPD0, tPD1
tCSMN
DO DATA VALID
Figure 2. Synchronous Data Timing
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CAT93C56 arduino
PIN # 1
IDENTIFICATION
TOP VIEW
CAT93C56, CAT93C57
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
θ
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.40
NOM
1.27 BSC
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
0.50
1.27
D
A1
A
eb
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
h
θ
L
END VIEW
c
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