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PDF CAT24C64 Data sheet ( Hoja de datos )
| Número de pieza | CAT24C64 | |
| Descripción | 64kb I2C CMOS Serial EEPROM | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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CAT24C64
64 Kb I2C CMOS Serial
EEPROM
Description
The CAT24C64 is a 64 Kb CMOS Serial EEPROM device,
internally organized as 8192 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
External address pins make it possible to address up to eight
CAT24C64 devices on the same bus.
Features
• Supports Standard, Fast and Fast−Plus I2C Protocol
• 1.7 V to 5.5 V Supply Voltage Range
• 32−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• PDIP, SOIC, TSSOP, US 8−lead, UDFN 8−pad and Ultra−thin
WLCSP 4−bump Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
VCC
SCL
A2, A1, A0
WP
CAT24C64
SDA
VSS
Figure 1. Functional Symbol
© Semiconductor Components Industries, LLC, 2015
November, 2016 − Rev. 25
1
www.onsemi.com
SOIC−8
W SUFFIX
CASE 751BD
UDFN−8
HU4 SUFFIX
CASE 517AZ
US8**
US SUFFIX
CASE 493
SOIC−8*
X SUFFIX
CASE 751BE
WLCSP−4
C4C SUFFIX
CASE 567JY
TSSOP−8
Y SUFFIX
CASE 948AL
WLCSP−4
C4U SUFFIX
CASE 567PB
PDIP−8
L SUFFIX
CASE 646AA
PIN CONFIGURATIONS (Top Views)
A0 1
A1
VCC
WP
1
VCC A1
A2 VSS
A2 SCL SCL B1 B2 SDA
VSS SDA
PDIP (L), SOIC (W, X),
US (US), TSSOP (Y),
UDFN (HU4)
WLCSP
(C4C)
(C4U)
MARKING
DIAGRAMS
(WLCSP−4)
X
YM
X
YW
X = Specific Device Code
= (see ordering information)
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
W = Production Week Code
For the location of Pin 1, please consult the
corresponding package drawing.
Pin Name
A0, A1, A2
SDA
SCL
WP
VCC
VSS
PIN FUNCTION
Function
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
* Not recommended for new designs
** Preliminary; please contact factory for availability
Publication Order Number:
CAT24C64/D
1 page  
SCL FROM
MASTER
CAT24C64
BUS RELEASE DELAY (TRANSMITTER)
18
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
ACK SETUP (≥ tSU:DAT)
SCL
tSU:STA
SDA IN
tF tHIGH
tLOW
tLOW
tHD:STA
tHD:DAT
tR
tSU:DAT
SDA OUT
tAA tDH
Figure 5. Bus Timing
tSU:STO
tBUF
WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
operation is in progress (tWR), the SDA output is tri−stated
and the Slave does not acknowledge the Master (Figure 7).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Delivery State
The CAT24C64 is shipped erased, i.e., all bytes are FFh.
www.onsemi.com
5
5 Page 
CAT24C64
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL MIN
NOM
MAX
A 1.20
A1 0.05
0.15
A2 0.80 0.90 1.05
E1 E
b 0.19
0.30
c 0.09
0.20
D 2.90 3.00 3.10
E 6.30 6.40 6.50
E1 4.30 4.40 4.50
e 0.65 BSC
L 1.00 REF
L1 0.50 0.60 0.75
θ 0º
8º
e
TOP VIEW
D
A2
A
q1
c
SIDE VIEW
A1
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
L1
END VIEW
L
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CAT24C64.PDF ] | |
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