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PDF NCP3135 Data sheet ( Hoja de datos )
| Número de pieza | NCP3135 | |
| Descripción | 5A Integrated Synchronous Buck Converter | |
| Fabricantes | ON Semiconductor | |
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NCP3135
5 A Integrated Synchronous
Buck Converter
NCP3135 is a fully integrated synchronous buck converter for 3.3 V
and 5 V step−down applications. It can provide up to 5 A DC load and
6 A instantaneous load current. NCP3135 supports high efficiency,
fast transient response and provides power good indicator. The control
scheme includes two operation modes: FCCM and automatic
CCM/DCM. In automatic CCM/DCM mode, the controller can
smoothly switch between CCM and DCM, where converter runs at
reduced switching frequency with much higher efficiency. NCP3135
is available in 3 mm x 3 mm QFN−16 pin package.
Features
• High Efficiency in both CCM and DCM
• High Operation Frequency at 1.1 MHz
• Support MLCC Output Capacitor
• Small Footprint, 3 mm x 3 mm, 16−pin QFN Package
• Up to 5 A Continuous Output Current
• 6 A Instantaneous Load Current
• 2.9 V to 5.5 V Wide Conversion Voltage Range
• Output Voltage Range from 0.6 V to 0.84 X Vin
• Internal 1 ms Soft−Start
• Automatic Power−Saving Mode
• Voltage Mode Control
• Support Pre-bias Start−up Functionality
• Output Discharge Operation
• Over−Temperature Protection
• Built−in Over−Voltage, Under−Voltage and Over-Current Protection
• Power Good Indicator
• This is a Pb−Free Device
Applications
• 5 V Step Down Rail
• 3.3 V Step Down Rail
www.onsemi.com
1
QFN16 3 x 3, 0.5P
CASE 485DA
SUGGESTED PIN ARRANGEMENT
PGND PGND VIN VIN
16 15 14 13
EN 1
12 VDD
NC 2
PGD 3
NCP3135
11 AGND
10 FB
VBST 4
9 COMP
5678
SW SW SW PS
MARKING DIAGRAM
3135
ALYWG
G
3135
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 1
1
Publication Order Number:
NCP3135/D
1 page  
NCP3135
Table 5. ELECTRICAL CHARACTERISTICS (VDD = VIN = 3.3 V and VDD = VIN = 5.0 V, TA = TJ = −40°C to 125°C.
Typical values are at TA = 25°C, PGND = GND unless otherwise noted)
Parameter
Symbol
Test Conditions
Min Typ Max
POWER SUPPLY
VIN operation voltage
VIN Nominal input voltage range
2.9 5.5
VIN UVLO threshold
Ramp up; EN = ‘HI’
2.8
VIN UVLO hysteresis
130
VDD internal bias voltage
Nominal 3.3 V input voltage range
2.9
5.5
VDD UVLO threshold
Ramp up; EN = ‘HI’
2.8
VDD UVLO hysteresis
75
VOLTAGE MONITOR
Power good low voltage
Pull−down voltage with 4 mA sink current
200 400
Power good high leakage current
−2.0 0
2.0
Power good threshold
Feedback lower voltage limit
80 83 86
Feedback higher voltage limit
114 117 120
Power good high delay
Minimum Vin voltage for valid PGD
at start up
tPGDELAY
Measured at Vin with 1 mA (or 2 mA) sink
current on PGD pin at start up
400
1
Output over-voltage protection
threshold at FB
114 117 120
Over-voltage blanking time
tOVPDLY Time from FB higher than 20% of Vref to 1.0 1.7 2.5
OVP fault
Output under-voltage protection
threshold at FB
80 83 86
Under-voltage blanking time
tUVPDLY
Time from FB lower than 20% of Vref to
UVP fault
11
SUPPLY CURRENT (TJ = +255C)
VDD quiescent current
IVDD EN = ‘HI’, no switching
2.2 3.5
VDD shutdown supply current
IVDD_SD
EN = ‘LO’
8.0
Vin shutdown supply current
IQSHDN EN = ‘LO’, Vin = 5 V
3.5
FEEDBACK VOLTAGE & ERROR AMPLIFIER
Reference voltage at FB
Unity gain bandwidth (Note 1)
VREF
−40°C < TA < 85°C
594 600 606
14
Open loop gain (Note 1)
80
FB pin leakage current
100
Output sourcing and sinking current
(Note 1)
Ccomp = 20 pF
5
Slew rate (Note 1)
5
OVER CURRENT PROTECTION & ZERO CROSSING
Over-current limit on high−side FET
One time over-current latch off on
the low−side FET
Zero crossing comparator internal
offset (Note 1)
When Iout exceeds this threshold for 4
consecutive cycles. Vin = 3.3 V, Vout =
1.5 V with 1 mH inductor, TA = +25°C
6.9 7.2 8.1
Immediately shut down when sensed cur-
rent reach this value. Vin = 3.3 V, Vout =
1.5 V with 1 mH inductor, TA = +25°C
7.0
8.1
PGND−SWN, Automatic CCM/DCM mode −4.5 −3.0 −1.5
Units
V
V
mV
V
V
mV
mV
mA
%Vref
%Vref
ms
V
%Vref
ms
%Vref
ms
mA
mA
mA
mV
MHz
dB
nA
mA
V/ ms
A
A
mV
www.onsemi.com
5
5 Page 
NCP3135
PROTECTIONS
Under Voltage Lockout (UVLO)
There is under-voltage lock out protection (UVLO) for
both VIN and VDD in NCP3135, which has a typical trip
threshold voltage 2.8 V and trip hysteresis 75 mV for VDD
and 130 mV for VIN. If UVLO is triggered, the device resets
and waits for the voltage to rise up over the threshold voltage
and restart the part. Please note this protection function
DOES NOT trigger the fault counter to latch off the part.
Over Voltage Protection (OVP)
When feedback voltage is above 17% (typical) of nominal
voltage for over 1.7 ms blanking time, an OV fault is set. In
this case, the converter de−asserts the PGD signal and
performs the over−voltage protection function. The top gate
drive is turned off and the bottom gate drive is turned on to
discharge the output. The bottom gate drive will be turned
off until VFB drops below the UVP threshold. The device
enters a high−impedance state. This protection is latched.
Under Voltage Protection (UVP)
Output under−voltage protection works in conjunction
with the current protection described in the Over−current
Protection sections. An UVP circuit monitors the feedback
voltage to detect under−voltage event. The under−voltage
limit is 17% (typical) below of nominal voltage at FB pin.
If the feedback voltage is below this threshold over 11 ms, an
UV fault is set and both the high−side and the low−side FETs
turn off. This protection is latched.
Power Good Monitor (PGD)
NCP3135 provides window comparator to monitor the
output voltage at FB pin. When the output voltage is within
±17% of regulation voltage, the power good pin outputs a
high signal. Otherwise, PGD stays low. The PGD pin is open
drain 5 mA pull down output. During startup, PGD stays low
until the feedback voltage is within the specified range for
about 0.4 ms. If feedback voltage falls outside the tolerance
band, the PG pin goes low after 10 ms delay.
The PGD pin de−asserts as soon as the EN pin is pulled
low or an under−voltage event on VDD is detected.
low−side FET exceeds 8.1 A, the over−current protection is
enabled and immediately turns off both the high−side and
the low−side FETs. The device is fully protected against
over−current during both on−time and off−time. This
protection is latched.
Pre−Bias Startup
In some applications the controller will be required to start
switching when its output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
This situation occurs for a number of reasons: the
converter’s output capacitors may have residual charge on
them or the converter’s output may be held up by a low
current standby power supply. NCP3135 supports pre−bias
start up by holding low−side FETs off until soft start ramp
reaches the FB pin voltage.
Thermal Shutdown
The NCP3135 protects itself from over heating with an
internal thermal monitoring circuit. When the die
temperature goes beyond a threshold value 135°C, both the
high−side and the low−side FETs turn off until the
temperature falls 40°C below of the threshold value. Then
the converter restarts.
Application Note
For higher output voltage application cases (Vout =
3.3 V), choose the inductor value not to be lower than 1 mH
to avoid over-current protection being triggered by inductor
current ripple; For Vin = 5 V and Vout = 3.3 V case, add a
voltage divider between Vin and EN to ensure that the part
can start up without triggering UVP. Use Figure 20 as design
reference for schematics. For other lower output voltage
cases, it is not necessary to add this divider.
VIN = 5 V
10 kW
Over Current Protection (OCP)
NCP3135 provides both high−side and low−side
MOSFET current limiting. When the current through the
high−side FET exceeds 7.5 A, the high−side FET turns off
and the low−side FET turns on until next PWM cycle. An
over−current counter is triggered and starts to increment
each occurrence of an over−current event. Both the
high−side and the low−side FETs turn off when the OC
counter reaches four. The OC counter resets if the detected
current is less than 7.5 A after an OC event.
Another set of over−current circuitry monitors the current
flowing through the low−side FET. If the current through the
3.6 kW
EN
PGND
Figure 20. Voltage divider between VIN and EN for
start−up in VIN = 5 V and VOUT = 3.3 V case
www.onsemi.com
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet NCP3135.PDF ] | |
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