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PDF NCP5230 Data sheet ( Hoja de datos )
| Número de pieza | NCP5230 | |
| Descripción | Precise Low Voltage Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP5230
Precise Low Voltage
Synchronous Buck
Controller with Power
Saving Mode
The NCP5230 is a simple single phase solution with differential
phase current sensing, power saving operation, and gate drivers to
provide accurately regulated power.
The adaptive non overlap gate drive and power saving operation
circuit provide a low switching loss and high efficiency solution for
server, notebook, and desktop systems. A high performance
operational error amplifier is provided to simplify compensation of the
system. The NCP5230 features also include soft−start sequence,
accurate overvoltage and over current protection, UVLO for VCC and
VCCP, and thermal shutdown.
Features
• High Performance Operational Error Amplifier
• Internal Soft−Start/Stop
• ±0.5% Internal Voltage Accuracy, 0.8 V voltage reference
• OCP accuracy, Four Re−entry Times Before Latch
• “Lossless” Differential Inductor Current Sensing
• Internal High Precision Current Sensing Amplifier
• Oscillator Frequency Range of 100 kHz − 1000 kHz
• 20 ns Adaptive FET Non−overlap Time of Internal Gate Driver
• 5.0 V to 12 V Operation
• Support 1.5 V to 19 V Vin
• Vout from 0.8 V to 3.3 V (5 V with 12 VCC)
• Chip Enable through OSC pin
• Latched Over Voltage Protection (OVP)
• Internally Fixed OCP Threshold
• Guaranteed Startup Into Pre−Charged Loads
• Thermally Compensated Current Monitoring
• Thermal Shutdown Protection
• Integrated MOSFET Drivers
• Integrated BOOST Diode with internal Rbst = 2.2 W
• Automatic Power Saving Mode to Maximize Efficiency During Light
Load Operation
• Sync Function
• Remote Ground Sensing
• This is a Pb−Free Device*
Applications
• Desktop and Server Systems
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
QFN16
5230
1
CASE 485G
ALYWG
G
5230
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
PIN CONNECTIONS
VCCP 1
LG 2
LX 3
BOOT 4
16 15 14 13
12 CSN/VO
11 FBG
10 VSEN
9 FB
5678
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
NCP5230MNTWG QFN16 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
January, 2013 − Rev. 1
1
Publication Order Number:
NCP5230/D
1 page  
NCP5230
ELECTRICAL CHARACTERISTICS Unless otherwise stated: 0°C < TA < 85°C; 4.5 V < VCC < 13.2 V; CVCC = 0.1 mF
Parameter
Test Conditions
Min Typ Max
OSCILLATOR (with no ROSC Resistor Defaults to 200 kHz)
Switching Frequency Accuracy
OSC Gain (Note 1)
ROSC open
−10
10
10
Disable threshold
MODULATORS (PWM Comparators)
ROSC/EN pin, Vdis_th
0.75
Minimum Pulse Width
Minimum Turn Off Time (LG on)
Magnitude of the PWM Ramp
Maximum Duty Cycle
Fsw = 200 kHz, OSC open
Fsw = 200 kHz, OSC open
VIN = 5 V or 12 V
OSC/EN = OPEN
90
250 350 450
1.50
80 95
Minimum Skip mode frequency
In light load, maximum time for LG to turn on
after HG turns off
30
SOFT−START
Soft Start Time @ 200 kHz
1024 clock cycles, OSC/EN open
5.12
SOFT−OFF
Soft OFF bleeding resistor
OVER CURRENT PROTECTION
Rdis
120
First Over Current Threshold
CSP−CSN, 4xMasking
17 20 23
Second Over Current Threshold
CSP−CSN, Immediate action
30
SYNC PIN
Synchronization Input
VIL, square wave
1.0
Synchronization Input
VIH, square wave
2.5
PROTECTION AND PGOOD
Output Voltage
Logic Low, Sinking 4 mA
0.4
OVP Threshold
UVP Threshold
Unlatched Overvoltage Threshold
Power Good High Delay (Note 1)
VSEN rising above 1.25 * Vref
VSEN falling below 0.75 * Vref
Vth_disoff with respect to 0.5 Vref
117 125 130
70 75 80
40 50 60
50
Power Good Low Delay (Note 1)
1
ZERO CURRENT DETECTION (LX Pin)
Blanking Time before Zero Current
Detection (Note 1)
Blanking Time after LG is < 1.0 V
40
Capture Time for LX Voltage (Note 1)
Time to capture LX voltage once LG is < 1.0 V
(must be within dead time limits)
20
Negative LX detection voltage
Positive LX detection voltage
Time for Vth adjustment and settling time
(Note 1)
Vbdls
Vbdhs
300 kHz
150 300 450
0.2 0.5 1.0
3.0 3.7
Unit
%
kHz /
mA
V
ns
ns
V
%
kHz
ms
W
mV
mV
V
V
V
%
%
%
ms
ms
ns
ns
mV
V
ms
Initial Negative Current Detection
Threshold Voltage Set Point (Note 1)
LX−GND, Includes ± 2 mV Offset Range
1.0 mV
Vth adjustable Range (Note 1)
−16 0
15 mV
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
http://onsemi.com
5
5 Page 
NCP5230
PWR
ON
Yes
EN> Vdis_th
No
VCC> POR &
VCCDR > UVLO _VCCDR (16−
pin )
UV (after Vout reaches UV
threshold in softstart )
UVP
PreOVP detection
VSEN >OV Vth
BG on
VCC > POR &
VCCDR > U_VLO VCCDR
No BOOT >UVLO_ BOOT
Yes
Fosc detection
OVP
Soft Start ,
Normal Operation
OCP, OVP, UVP detection
OV
OC
OCP
4 times
reentry
TG OFF, BG
OFF
PGOOD= 0
No
TG OFF, BG ON
PGOOD =0
Vout < Vth_disoff
Yes
After 4 times reentry for
1st threshod
or immediately over 2nd
threshold
TG OFF, BG
OFF
Yes OVP
No
Vo discharge
mode
Vcc<UVLO_Vcc, Or
EN<Vdis_th Or
Boot<UVLO_Boot
No
Figure 8. State Diagram
http://onsemi.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NCP5230.PDF ] | |
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