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Número de pieza | NCP81149 | |
Descripción | Single-Phase Voltage Regulator | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! NCP81149
Single-Phase Voltage
Regulator with SVID
Interface for Computing
Applications
High Switching Frequency, High
Efficiency, Integrated Power MOSFETs
The NCP81149, a single−phase synchronous buck regulator,
integrates power MOSFETs to provide a high−efficiency and
compact−footprint power management solution for new generation
computing CPUs. The device is able to deliver up to 14 A TDC output
current on an adjustable output with SVID interface. Operating in high
switching frequency up to 1.2 MHz allows employing small size
inductors and capacitors while maintaining high efficiency due to
integrated solution with high performance power MOSFETs.
Current−mode RPM control with feedforward from both input power
supply and output voltage ensures stable operation over wide
operation condition. The NCP81149 is in a QFN48 6 x 6 mm package.
Features
• Meets Intel® VR12.6 and VR12.6+ Specifications
• Support 11.5 W and 15 W ULT Platforms
• 4.5 V to 25 V Input Voltage Range
• Adjustable Output Voltage with SVID Interface
• Integrated Gate Driver and Power MOSFETs
• 0 V, 1.65 V, 1.7 V, 1.75 V Boot Up Voltage
• 500 kHz ~ 1.2 MHz Switching Frequency
• Current−Mode RPM Control
• Adaptive Voltage Positioning (AVP)
• Programmable DVID Feed−Forward to Support Fast DVID
• Feedforward Operation for Input Supply Voltage and Output Voltage
• Output Over−Voltage and Under−Voltage Protections
• External Current Limitation Programming with Inductor Current
Sense
• QFN48, 6x6 mm, 0.4 mm Pitch Package
• This is a Pb−Free Device
Typical Applications
• Ultrabook Applications
• Notebook Applications
www.onsemi.com
1 48
QFN48
CASE 485CJ
MARKING
DIAGRAM
1
NCP81149
AWLYYWWG
NCP81149 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package Shipping†
NCP81149MNTXG
QFN48 2500 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 2
1
Publication Order Number:
NCP81149/D
1 page NCP81149
PIN DESCRIPTION
Pin Name
47 VCC
Type
Analog Power
48 EN
Logic Input
Description
Voltage Supply of Controller. Power supply input pin of control circuits. A 1 mF or larger
ceramic capacitor bypasses this input to ground. This capacitor should be placed as close
as possible to this pin.
Enable. Logic high enables the device and logic low makes the device in standby mode.
MAXIMUM RATINGS
Value
Power Supply Voltage to PGND
Switch Node to PGND
Analog Supply Voltage to GND
BST to PGND
Rating
Symbol
VVIN
VSW
VCC, VCCP
BST_PGND
Min Max Unit
30 V
30 V
−0.3 6.5 V
−0.3 33 V
38 (<50 ns)
BST to SW
BST_SW
−0.3
6.5 V
GH to SW
GH
−0.3
BST + 0.3
V
−2 (<200 ns)
GL to GND
GL
−0.3
VCCP + 0.3
V
−2 (<200 ns)
VSN to GND
VSN −0.3 0.3 V
IOUT
IOUT −0.3 2.5 V
PGND to GND
PGND
−0.3
0.3 V
Other Pins
Latch up Current: (Note 1)
All pins, except digital pins
Digital pins
−0.3
VCC + 0.3
V
ILU mA
−100
100
−10 10
Operating Junction Temperature Range
TJ −40 150 °C
Operating Ambient Temperature Range
TA −40 125 °C
Storage Temperature Range
TSTG −55 150 °C
Thermal Resistance Junction to Board (Note 2)
RθJB
8.2 °C/W
Thermal Resistance Junction to Ambient (Note 2)
RθJA
21.8 °C/W
Power Dissipation at TA = 25°C (Note 3)
PD 4.59 W
Moisture Sensitivity Level (Note 4)
MSL
3−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Latch up Current per JEDEC standard: JESD78 class II.
2. The thermal resistance values are dependent of the internal losses split between devices and the PCB heat dissipation. This data is based
on a typical operation condition with a 4−layer FR−4 PCB board, which has two, 1−ounce copper internal power and ground planes and
2−ounce copper traces on top and bottom layers with approximately 80% copper coverage. No airflow and no heat sink applied (reference
EIA/JEDEC 51.7). It also does not account for other heat sources that may be present on the PCB next to the device in question (such as
inductors, resistors etc.)
3. The maximum power dissipation (PD) is dependent on input voltage, output voltage, output current, external components selected, and PCB
layout. The reference data is obtained based on TJMAX = 125°C and RθJA = 21.8°C/W.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
www.onsemi.com
5
5 Page Table 2. VR12.6 VID CODES
VID7
VID6
VID5
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 00
0 01
0 01
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
NCP81149
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Voltage (V)
OFF
0.5
0.51
0.52
0.53
0.54
0.55
0.56
0.57
0.58
0.59
0.6
0.61
0.62
0.63
0.64
0.65
0.66
0.67
0.68
0.69
0.7
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.8
0.81
0.82
HEX
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
www.onsemi.com
11
11 Page |
Páginas | Total 24 Páginas | |
PDF Descargar | [ Datasheet NCP81149.PDF ] |
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