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PDF ILI9328 Data sheet ( Hoja de datos )
| Número de pieza | ILI9328 | |
| Descripción | a-Si TFT LCD Single Chip Driver | |
| Fabricantes | ILI TECHNOLOGY | |
| Logotipo |  |
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ILI9328
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
Datasheet
Version: V0.15
Document No.: ILI9328DS_V0.15.pdf
ILI TECHNOLOGY CORP.
8F, No.38, Taiyuan St., Jhubei City, Hsinchu County,
Taiwan 302, R.O.C.
Tel.886-3-5600099; Fax.886-3-5630525
http://www.ilitek.com
1 page  
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9328
Figures
FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION .................................................................................... 24
FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 25
FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT ......................................................................................................... 26
FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 27
FIGURE5 8-BIT SYSTEM INTERFACE DATA FORMAT ........................................................................................................... 28
FIGURE6 DATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE.................................................................. 28
FIGURE 7 DATA FORMAT OF SPI INTERFACE..................................................................................................................... 30
FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) ............................................................... 31
FIGURE9 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI=”1” AND DFM=”10”).................... 32
FIGURE10 DATA TRANSMISSION THROUGH VSYNC INTERFACE)....................................................................................... 33
FIGURE11 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE ............................................................ 33
FIGURE12 OPERATION THROUGH VSYNC INTERFACE ...................................................................................................... 34
FIGURE13 TRANSITION FLOW BETWEEN VSYNC AND INTERNAL CLOCK OPERATION MODES ............................................ 36
FIGURE14 RGB INTERFACE DATA FORMAT ...................................................................................................................... 37
FIGURE15 GRAM ACCESS AREA BY RGB INTERFACE ..................................................................................................... 38
FIGURE16 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE.................................................................. 39
FIGURE17 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE ............................................................................ 40
FIGURE18 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE.................................................................................... 41
FIGURE19 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING ................................................................... 44
FIGURE20 GRAM ACCESS BETWEEN SYSTEM INTERFACE AND RGB INTERFACE .............................................................. 45
FIGURE21 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL ..................................... 46
FIGURE22 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI)...................................................................... 47
FIGURE23 REGISTER SETTING WITH I80 SYSTEM INTERFACE ............................................................................................ 48
FIGURE 24 REGISTER READ/WRITE TIMING OF I80 SYSTEM INTERFACE ........................................................................... 49
FIGURE25 GRAM ACCESS DIRECTION SETTING ............................................................................................................... 54
FIGURE28 16-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................. 55
FIGURE29 8-BIT MPU SYSTEM INTERFACE DATA FORMAT............................................................................................... 56
FIGURE 30 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE.............. 67
FIGURE 31 GRAM DATA READ BACK FLOW CHART ........................................................................................................ 68
FIGURE 32 GRAM ACCESS RANGE CONFIGURATION ........................................................................................................ 71
FIGURE33 GRAM READ/WRITE TIMING OF I80-SYSTEM INTERFACE ............................................................................... 77
FIGURE34 I80-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=”0”, BGR=”0”) ................................................. 79
FIGURE35 I80-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=”0”, BGR=”0”) .............................................................. 80
FIGURE 36 I80-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS=”1”, BGR=”1”) ....................................................... 82
FIGURE 37 GRAM ACCESS WINDOW MAP ....................................................................................................................... 83
FIGURE 38 GRAYSCALE VOLTAGE GENERATION............................................................................................................... 84
FIGURE 39 GRAYSCALE VOLTAGE ADJUSTMENT .............................................................................................................. 85
FIGURE 40 GAMMA CURVE ADJUSTMENT ......................................................................................................................... 86
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 5 of 104
5 Page 
a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9328
Pin Name
I/O Type
Descriptions
16-bit RGB I/F: DB[17:13] and DB[11:1] are used.
18-bit RGB I/F: DB[17:0] are used.
ENABLE
Unused pins must be fixed to GND level.
Data ENEABLE signal for RGB interface operation.
Low: Select (access enabled)
I
MPU
IOVcc
High: Not select (access inhibited)
The EPL bit inverts the polarity of the ENABLE signal.
DOTCLK
VSYNC
HSYNC
FMARK
S720~S1
G320~G1
VCOM
VCOMH
VCOML
VGS
Vci
GND
Vci1
DDVDH
Fix to either IOVcc or GND level when not in use.
Dot clock signal for RGB interface operation.
I
MPU
IOVcc
DPL = “0”: Input data on the rising edge of DOTCLK
DPL = “1”: Input data on the falling edge of DOTCLK
Fix to the GND level when not in use
Frame synchronizing signal for RGB interface operation.
I
MPU
IOVcc
VSPL = “0”: Active low.
VSPL = “1”: Active high.
Fix to the GND level when not in use.
Line synchronizing signal for RGB interface operation.
I
MPU
IOVcc
HSPL = “0”: Active low.
HSPL = “1”: Active high.
Fix to the GND level when not in use
O
MPU
IOVcc
Output a frame head pulse signal.
The FMARK signal is used when writing RAM data in synchronization
with frame. Leave the pin open when not in use.
LCD Driving signals
Source output voltage signals applied to liquid crystal.
To change the shift direction of signal outputs, use the SS bit.
O LCD
SS = “0”, the data in the RAM address “h00000” is output from S1.
SS = “1”, the data in the RAM address “h00000” is output from S720.
S1, S4, S7, … display red (R), S2, S5, S8, ... display green (G), and
S3, S6, S9, ... display blue (B) (SS = 0).
Gate line output signals.
O LCD
VGH: the level selecting gate lines
VGL: the level not selecting gate lines
TFT A supply voltage to the common electrode of TFT panel.
O common VCOM is AC voltage alternating signal between the VCOMH and
electrode VCOML levels.
O
Stabilizing The high level of VCOM AC voltage. Connect to a stabilizing
capacitor capacitor.
O
Stabilizing The low level of VCOM AC voltage. Adjust the VCOML level with the
capacitor VDV bits. Connect to a stabilizing capacitor.
I
GND or
external
resistor
Reference level for the grayscale voltage generating circuit. The VGS
level can be changed by connecting to an external resistor.
Charge-pump and Regulator Circuit
I
Power
supply
A supply voltage to the analog circuit. Connect to an external power
supply of 2.5 ~ 3.3V.
I
Power
supply
GND for the analog side: GND = 0V. In case of COG, connect to
GND on the FPC to prevent noise.
An internal reference voltage for the step-up circuit1.
O
Stabilizing
capacitor
The amplitude between Vci and GND is determined by the VC[2:0]
bits.
Make sure to set the Vci1 voltage so that the DDVDH, VGH and VGL
voltages are set within the respective specification.
O Stabilizing Power supply for the source driver and Vcom drive.
The information contained herein is the exclusive property of ILI Technology Corp. and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp.
Page 11 of 104
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ILI9328.PDF ] | |
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